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289024fd89
- Creating an arbitrary 'src' directory really doesn't help much... - Goal is to make each folder self contained - Make meta repos and individual repos have the same directory structure
270 lines
7.5 KiB
Verilog
270 lines
7.5 KiB
Verilog
/* verilator lint_off STMTDLY */
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/* verilator lint_off WIDTH */
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module PLLE2_ADV #(
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parameter BANDWIDTH = "OPTIMIZED",
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parameter integer CLKFBOUT_MULT = 5,
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parameter real CLKFBOUT_PHASE = 0.000,
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parameter real CLKIN1_PERIOD = 0.000,
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parameter real CLKIN2_PERIOD = 0.000,
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parameter integer CLKOUT0_DIVIDE = 1,
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parameter real CLKOUT0_DUTY_CYCLE = 0.500,
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parameter real CLKOUT0_PHASE = 0.000,
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parameter integer CLKOUT1_DIVIDE = 1,
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parameter real CLKOUT1_DUTY_CYCLE = 0.500,
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parameter real CLKOUT1_PHASE = 0.000,
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parameter integer CLKOUT2_DIVIDE = 1,
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parameter real CLKOUT2_DUTY_CYCLE = 0.500,
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parameter real CLKOUT2_PHASE = 0.000,
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parameter integer CLKOUT3_DIVIDE = 1,
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parameter real CLKOUT3_DUTY_CYCLE = 0.500,
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parameter real CLKOUT3_PHASE = 0.000,
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parameter integer CLKOUT4_DIVIDE = 1,
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parameter real CLKOUT4_DUTY_CYCLE = 0.500,
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parameter real CLKOUT4_PHASE = 0.000,
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parameter integer CLKOUT5_DIVIDE = 1,
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parameter real CLKOUT5_DUTY_CYCLE = 0.500,
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parameter real CLKOUT5_PHASE = 0.000,
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parameter COMPENSATION = "ZHOLD",
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parameter integer DIVCLK_DIVIDE = 1,
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parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0,
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parameter [0:0] IS_PWRDWN_INVERTED = 1'b0,
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parameter [0:0] IS_RST_INVERTED = 1'b0,
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parameter real REF_JITTER1 = 0.010,
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parameter real REF_JITTER2 = 0.010,
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parameter STARTUP_WAIT = "FALSE"
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)(
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output CLKOUT0,
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output CLKOUT1,
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output CLKOUT2,
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output CLKOUT3,
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output CLKOUT4,
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output CLKOUT5,
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output [15:0] DO,
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output DRDY,
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output LOCKED,
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output CLKFBOUT,
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input CLKFBIN,
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input CLKIN1,
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input CLKIN2,
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input CLKINSEL,
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input [6:0] DADDR,
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input DCLK,
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input DEN,
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input [15:0] DI,
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input DWE,
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input PWRDWN,
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input RST
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);
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//#LOCAL DERIVED PARAMETERS
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localparam real VCO_PERIOD = (CLKIN1_PERIOD * DIVCLK_DIVIDE) / CLKFBOUT_MULT;
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localparam real CLK0_DELAY = VCO_PERIOD * CLKOUT0_DIVIDE * (CLKOUT0_PHASE/360);
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localparam real CLK1_DELAY = VCO_PERIOD * CLKOUT1_DIVIDE * (CLKOUT1_PHASE/360);
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localparam real CLK2_DELAY = VCO_PERIOD * CLKOUT2_DIVIDE * (CLKOUT2_PHASE/360);
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localparam real CLK3_DELAY = VCO_PERIOD * CLKOUT3_DIVIDE * (CLKOUT3_PHASE/360);
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localparam real CLK4_DELAY = VCO_PERIOD * CLKOUT4_DIVIDE * (CLKOUT4_PHASE/360);
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localparam real CLK5_DELAY = VCO_PERIOD * CLKOUT5_DIVIDE * (CLKOUT5_PHASE/360);
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localparam phases = CLKFBOUT_MULT / DIVCLK_DIVIDE;
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//########################################################################
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//# POR
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//########################################################################
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//ugly POR reset
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reg POR;
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initial
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begin
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POR=1'b1;
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#1
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POR=1'b0;
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end
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//async reset
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wire reset;
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assign reset = POR | RST;
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//########################################################################
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//# CLOCK MULTIPLIER
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//########################################################################
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//TODO: implement DIVCLK_DIVIDE
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//
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integer j;
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reg [2*phases-1:0] delay;
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always @ (CLKIN1 or reset)
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if(reset)
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for(j=0; j<(2*phases); j=j+1)
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delay[j] <= 1'b0;
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else
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for(j=0; j<(2*phases); j=j+1)
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delay[j] <= #(CLKIN1_PERIOD*j/(2*phases)) CLKIN1;
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reg [(phases)-1:0] clk_comb;
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always @ (delay)
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begin
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for(j=0; j<(phases); j=j+1)
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clk_comb[j] <= ~reset & delay[2*j] & ~delay[2*j+1];
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end
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reg vco_clk;
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integer k;
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always @*
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begin
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vco_clk = 1'b0;
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for(k=0; k<(phases); k=k+1)
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vco_clk = vco_clk | clk_comb[k];
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end
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//##############
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//#DIVIDERS
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//##############
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wire [3:0] DIVCFG[5:0];
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wire [5:0] CLKOUT_DIV;
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assign DIVCFG[0] = $clog2(CLKOUT0_DIVIDE);
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assign DIVCFG[1] = $clog2(CLKOUT1_DIVIDE);
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assign DIVCFG[2] = $clog2(CLKOUT2_DIVIDE);
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assign DIVCFG[3] = $clog2(CLKOUT3_DIVIDE);
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assign DIVCFG[4] = $clog2(CLKOUT4_DIVIDE);
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assign DIVCFG[5] = $clog2(CLKOUT5_DIVIDE);
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genvar i;
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generate for(i=0; i<6; i=i+1)
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begin : gen_clkdiv
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CLKDIV clkdiv (// Outputs
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.clkout (CLKOUT_DIV[i]),
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// Inputs
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.clkin (vco_clk),
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.divcfg (DIVCFG[i]),
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.reset (reset));
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end
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endgenerate
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reg [5:0] CLKOUT_DIV_LOCK;
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`ifdef TARGET_VERILATOR
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initial
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begin
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$display("ERROR: PLL divider not implemented");
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end
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`else
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always @ (posedge (CLKIN1 & vco_clk) or negedge (CLKIN1&~vco_clk))
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begin
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CLKOUT_DIV_LOCK[5:0] = CLKOUT_DIV[5:0];
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end
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`endif
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//##############
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//#SUB PHASE DELAY
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//##############
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reg CLKOUT0;
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reg CLKOUT1;
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reg CLKOUT2;
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reg CLKOUT3;
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reg CLKOUT4;
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reg CLKOUT5;
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always @ (CLKOUT_DIV_LOCK)
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begin
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CLKOUT0 = #(CLK0_DELAY) ~reset & CLKOUT_DIV_LOCK[0];
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CLKOUT1 = #(CLK1_DELAY) ~reset & CLKOUT_DIV_LOCK[1];
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CLKOUT2 = #(CLK2_DELAY) ~reset & CLKOUT_DIV_LOCK[2];
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CLKOUT3 = #(CLK3_DELAY) ~reset & CLKOUT_DIV_LOCK[3];
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CLKOUT4 = #(CLK4_DELAY) ~reset & CLKOUT_DIV_LOCK[4];
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CLKOUT5 = #(CLK5_DELAY) ~reset & CLKOUT_DIV_LOCK[5];
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end
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//##############
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//#DUMMY DRIVES
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//##############
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assign CLKFBOUT=CLKIN1;
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//###########################
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//#SANITY CHECK LOCK COUNTER
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//############################
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localparam LCW=4;
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reg [LCW-1:0] lock_counter;
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always @ (posedge CLKIN1 or posedge reset)
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if(reset)
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lock_counter[LCW-1:0] <= {(LCW){1'b1}};
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else if(~LOCKED)
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lock_counter[LCW-1:0] <= lock_counter[LCW-1:0] - 1'b1;
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assign LOCKED = ~(|lock_counter[LCW-1:0]);
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endmodule // PLLE2_ADV
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// Local Variables:
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// verilog-library-directories:("." "../../common/hdl")
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// End:
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// ###############################################################
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// # FUNCTION: Synchronous clock divider that divides by integer
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// ###############################################################
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module oh_clockdiv_model(/*AUTOARG*/
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// Outputs
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clkout,
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// Inputs
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clkin, divcfg, reset
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);
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input clkin; // Input clock
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input [3:0] divcfg; // Divide factor (1-128)
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input reset; // Counter init
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output clkout; // Divided clock phase aligned with clkin
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reg clkout_reg;
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reg [7:0] counter;
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reg [7:0] divcfg_dec;
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reg [3:0] divcfg_reg;
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wire div_bp;
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wire posedge_match;
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wire negedge_match;
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// ###################
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// # Decode divcfg
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// ###################
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always @ (divcfg[3:0])
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casez (divcfg[3:0])
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4'b0001 : divcfg_dec[7:0] = 8'b00000010; // Divide by 2
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4'b0010 : divcfg_dec[7:0] = 8'b00000100; // Divide by 4
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4'b0011 : divcfg_dec[7:0] = 8'b00001000; // Divide by 8
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4'b0100 : divcfg_dec[7:0] = 8'b00010000; // Divide by 16
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4'b0101 : divcfg_dec[7:0] = 8'b00100000; // Divide by 32
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4'b0110 : divcfg_dec[7:0] = 8'b01000000; // Divide by 64
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4'b0111 : divcfg_dec[7:0] = 8'b10000000; // Divide by 128
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default : divcfg_dec[7:0] = 8'b00000000; // others
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endcase
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always @ (posedge clkin or posedge reset)
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if(reset)
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counter[7:0] <= 8'b00000001;
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else if(posedge_match)
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counter[7:0] <= 8'b00000001;// Self resetting
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else
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counter[7:0] <= (counter[7:0] + 8'b00000001);
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assign posedge_match = (counter[7:0]==divcfg_dec[7:0]);
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assign negedge_match = (counter[7:0]=={1'b0,divcfg_dec[7:1]});
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always @ (posedge clkin or posedge reset)
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if(reset)
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clkout_reg <= 1'b0;
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else if(posedge_match)
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clkout_reg <= 1'b1;
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else if(negedge_match)
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clkout_reg <= 1'b0;
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//Divide by one bypass
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assign div_bp = (divcfg[3:0]==4'b0000);
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assign clkout = div_bp ? clkin : clkout_reg;
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endmodule // oh_clockdiv
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