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fd7aff5dd8
- Don't fight the tools - No way to remove these warnings and I don't want to have to tell everyone to include maging "don't output this kind of warning flags" that are global to a project...that's just bad practice. - Didn't take many minutes to remove these warnings and now synthesis runs through with 0 warnings ... much cleaner.. inspires more confidence
43 lines
871 B
Verilog
43 lines
871 B
Verilog
/* Simple combinatorial priority arbiter
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* bit[0] has highest priority
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*
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*/
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module oh_arbiter(/*AUTOARG*/
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// Outputs
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grants,
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// Inputs
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requests
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);
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parameter N = 99;
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parameter TYPE = "FIXED"; //arbiter type
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//"FIXED"
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//"ROUNDROBIN"
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//"FAIR"
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input [N-1:0] requests; //request vector
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output [N-1:0] grants; //grant (one hot)
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wire [N-1:0] waitmask;
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genvar j;
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generate
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if(TYPE=="FIXED")
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begin : arbiter_fixed
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assign waitmask[0] = 1'b0;
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for (j=N-1; j>=1; j=j-1)
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begin : gen_arbiter
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assign waitmask[j] = |requests[j-1:0];
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end
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end
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endgenerate
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//grant circuit
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assign grants[N-1:0] = requests[N-1:0] & ~waitmask[N-1:0];
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endmodule // oh_arbiter
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