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57 lines
1.2 KiB
Verilog
57 lines
1.2 KiB
Verilog
/*
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* ---- E4 PACKET FORMAT (104 bits) ----
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* [0] write bit
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* [2:1] datamode
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* [6:3] ctrlmode
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* [7] reserved
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* [39:8] f0 = dstaddr(lo)
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* [71:40] f1 = data (lo)
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* [103:72] f2 = srcaddr(lo) / data (hi)
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*
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*/
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module packet2emesh(/*AUTOARG*/
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// Outputs
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write_in, datamode_in, ctrlmode_in, dstaddr_in, srcaddr_in,
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data_in,
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// Inputs
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packet_in
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);
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parameter AW = 32;
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parameter PW = (2*AW+40);
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//Input packet
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input [PW-1:0] packet_in;
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//Emesh signal bundle
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output write_in;
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output [1:0] datamode_in;
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output [4:0] ctrlmode_in;
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output [AW-1:0] dstaddr_in;
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output [AW-1:0] srcaddr_in;
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output [AW-1:0] data_in;
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generate
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if(AW==32 & PW==104)
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begin
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assign write_in = packet_in[0];
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assign datamode_in[1:0] = packet_in[2:1];
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assign ctrlmode_in[4:0] = {1'b0,packet_in[6:3]};
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assign dstaddr_in[31:0] = packet_in[39:8];
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assign srcaddr_in[31:0] = packet_in[103:72];
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assign data_in[63:0] = packet_in[103:40];
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end
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else
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begin
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initial
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$display ("Only AW=32 and PW=104 is supported");
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end
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endgenerate
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endmodule // packet2emesh
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