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53 lines
1.7 KiB
Verilog
53 lines
1.7 KiB
Verilog
/*Converts an emesh bundle into a 104 bit packet*/
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module emesh2packet(/*AUTOARG*/
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// Outputs
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packet_out,
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// Inputs
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access_in, write_in, datamode_in, ctrlmode_in, dstaddr_in, data_in,
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srcaddr_in
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);
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parameter AW=32;
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parameter DW=32;
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parameter PW=104;
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//Emesh signal bundle
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input access_in;
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input write_in;
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input [1:0] datamode_in;
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input [3:0] ctrlmode_in;
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input [AW-1:0] dstaddr_in;
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input [DW-1:0] data_in;
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input [AW-1:0] srcaddr_in;
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//Output packet
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output [PW-1:0] packet_out;
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assign packet_out[0] = access_in;
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assign packet_out[1] = write_in;
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assign packet_out[3:2] = datamode_in[1:0];
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assign packet_out[7:4] = ctrlmode_in[7:4];
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assign packet_out[39:8] = dstaddr_in[AW-1:0];
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assign packet_out[71:40] = data_in[AW-1:0];
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assign packet_out[103:72] = srcaddr_in[AW-1:0];
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endmodule // emesh2packet
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/*
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Copyright (C) 2015 Adapteva, Inc.
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Contributed by Andreas Olofsson <support@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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