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117 lines
3.2 KiB
Verilog
117 lines
3.2 KiB
Verilog
module dut(/*AUTOARG*/
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// Outputs
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dut_active, wait_out, access_out, packet_out,
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// Inputs
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core_packet, core_access, clk, clk1, clk2, nreset, vdd, vss,
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clkout, access_in, packet_in, wait_in
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);
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parameter SREGS = 40;
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parameter AW = 32;
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parameter DW = 32;
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parameter CW = 2;
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parameter IDW = 12;
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parameter M_IDW = 6;
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parameter S_IDW = 12;
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parameter PW = 104;
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parameter N = 1;
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//#######################################
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//# CLOCK AND RESET
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//#######################################
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input clk1;
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input clk2;
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input nreset;
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input [N*N-1:0] vdd;
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input vss;
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output dut_active;
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output clkout;
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//#######################################
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//#EMESH INTERFACE
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//#######################################
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//Stimulus Driven Transaction
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input [N-1:0] access_in;
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input [N*PW-1:0] packet_in;
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output [N-1:0] wait_out;
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//DUT driven transaction
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output [N-1:0] access_out;
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output [N*PW-1:0] packet_out;
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input [N-1:0] wait_in;
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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input clk; // To spi_master of spi_master.v, ...
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input core_access; // To spi_slave of spi_slave.v
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input [PW-1:0] core_packet; // To spi_slave of spi_slave.v
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// End of automatics
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire core_spi_access; // From spi_slave of spi_slave.v
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wire [PW-1:0] core_spi_packet; // From spi_slave of spi_slave.v
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wire core_spi_wait; // From spi_slave of spi_slave.v
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wire miso; // From spi_slave of spi_slave.v
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wire mosi; // From spi_master of spi_master.v
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wire sclk; // From spi_master of spi_master.v
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wire [SREGS*8-1:0] spi_regs; // From spi_slave of spi_slave.v
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wire ss; // From spi_master of spi_master.v
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// End of automatics
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//###################
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// GLUE
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//###################
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assign clkout = clk1;
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assign clk = clk1;
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assign wait_out = 1'b0;
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assign dut_active = 1'b1;
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//######################################################################
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//# DUT
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//######################################################################
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spi_master #(.AW(AW))
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spi_master (/*AUTOINST*/
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// Outputs
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.sclk (sclk),
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.mosi (mosi),
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.ss (ss),
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.wait_out (wait_out),
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.access_out (access_out),
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.packet_out (packet_out[PW-1:0]),
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// Inputs
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.clk (clk),
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.nreset (nreset),
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.miso (miso),
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.access_in (access_in),
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.packet_in (packet_in[PW-1:0]),
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.wait_in (wait_in));
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spi_slave #(.AW(AW),
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.SREGS(SREGS)
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)
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spi_slave (/*AUTOINST*/
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// Outputs
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.spi_regs (spi_regs[SREGS*8-1:0]),
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.miso (miso),
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.core_spi_access (core_spi_access),
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.core_spi_packet (core_spi_packet[PW-1:0]),
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.core_spi_wait (core_spi_wait),
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// Inputs
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.clk (clk),
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.nreset (nreset),
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.sclk (sclk),
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.mosi (mosi),
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.ss (ss),
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.core_access (core_access),
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.core_packet (core_packet[PW-1:0]));
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endmodule // dut
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// Local Variables:
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// verilog-library-directories:("." "../hdl" "../../emesh/hdl")
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// End:
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