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277 lines
9.2 KiB
Verilog
277 lines
9.2 KiB
Verilog
`include "elink_regmap.v"
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module erx_cfg (/*AUTOARG*/
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// Outputs
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dma_access, mailbox_access, ecfg_access, ecfg_packet, mmu_enable,
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remap_mode, remap_base, remap_pattern, remap_sel, idelay_value,
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load_taps, test_mode, mailbox_irq_en,
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// Inputs
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nreset, clk, erx_cfg_access, erx_cfg_packet, edma_rdata,
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mailbox_rdata, erx_access, erx_packet, gpio_datain, rx_status
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);
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//##################################################################
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//# INTERFACE
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//##################################################################
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parameter AW = 32; // address width
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localparam PW = 2*AW+40; // packet width
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localparam RFAW = 6; // register block size
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//reset+clk
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input nreset; // async active low reset
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input clk; // slow clock
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//packet input
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input erx_cfg_access; // access from TX
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input [PW-1:0] erx_cfg_packet; // packet
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//readback/decode
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output dma_access; // dma access
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output mailbox_access; // mailbox access
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input [31:0] edma_rdata; // dma readback data
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input [31:0] mailbox_rdata; // mailbox readback data
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//output packet
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output ecfg_access; // access signal for axi_slave
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output [PW-1:0] ecfg_packet; // readback data for axi_slave
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//rx config
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output mmu_enable; // enables MMU on rx path (static)
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output [1:0] remap_mode; // remap mode (static)
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output [31:0] remap_base; // base for dynamic remap (static)
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output [11:0] remap_pattern; // patter for static remap (static)
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output [11:0] remap_sel; // selects for static remap (static)
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output [44:0] idelay_value; // tap values for erx idelay
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output load_taps; // loads the idelay_value into IDELAY prim
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output test_mode; // testmode blocks all rx ports to fifo
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output mailbox_irq_en; // irq enable for mailbox
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//rx debug packets
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input erx_access; // rx raw access for debug
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input [PW-1:0] erx_packet; // rx raw packet for debug
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//status signals
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input [8:0] gpio_datain; // frame and data inputs (static)
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input [15:0] rx_status; // etx status signals
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//##################################################################
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//# BODY
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//##################################################################
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//registers
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reg [31:0] rx_cfg_reg;
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reg [31:0] rx_offset_reg;
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reg [8:0] rx_gpio_reg;
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reg [15:0] rx_status_reg;
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reg [31:0] rx_testdata_reg;
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reg [44:0] idelay;
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reg load_taps;
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reg [31:0] cfg_rdata;
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reg [AW-1:0] data_out;
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reg [AW-1:0] dstaddr_out;
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reg [AW-1:0] srcaddr_out;
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reg write_out;
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reg [4:0] ctrlmode_out;
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reg [1:0] datamode_out;
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reg ecfg_access;
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reg rx_sel;
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reg dma_sel;
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reg mailbox_sel;
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reg tx_sel;
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wire [31:0] data_mux;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [4:0] ctrlmode_in; // From p2e of packet2emesh.v
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wire [AW-1:0] data_in; // From p2e of packet2emesh.v
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wire [1:0] datamode_in; // From p2e of packet2emesh.v
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wire [AW-1:0] dstaddr_in; // From p2e of packet2emesh.v
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wire [AW-1:0] srcaddr_in; // From p2e of packet2emesh.v
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wire write_in; // From p2e of packet2emesh.v
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// End of automatics
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//#################################
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//# PACKET DECODE
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//#################################
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packet2emesh #(.AW(AW))
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p2e (.packet_in (erx_cfg_packet[PW-1:0]),
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/*AUTOINST*/
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// Outputs
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.write_in (write_in),
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.datamode_in (datamode_in[1:0]),
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.ctrlmode_in (ctrlmode_in[4:0]),
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.dstaddr_in (dstaddr_in[AW-1:0]),
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.srcaddr_in (srcaddr_in[AW-1:0]),
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.data_in (data_in[AW-1:0]));
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//read/write decode
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assign cfg_access = erx_cfg_access &
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(dstaddr_in[19:16] ==`EGROUP_MMR) &
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(dstaddr_in[10:8] ==`EGROUP_RX) &
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~dstaddr_in[5]; //reserveed for mailbox
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assign mailbox_access = erx_cfg_access &
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(dstaddr_in[19:16] ==`EGROUP_MMR) &
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(dstaddr_in[10:8] ==`EGROUP_RX) &
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dstaddr_in[5];
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assign dma_access = erx_cfg_access &
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(dstaddr_in[19:16] ==`EGROUP_MMR) &
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(dstaddr_in[10:8] ==`EGROUP_DMA);
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//Read operation (cfg or dma or mailbox)
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assign ecfg_read = erx_cfg_access & ~write_in;
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//Write to the register file
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assign ecfg_write = cfg_access & write_in;
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//Passing through readback data from TX
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assign ecfg_tx_read = erx_cfg_access &
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(dstaddr_in[19:16] ==`EGROUP_RR);
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//Config write enables
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assign rx_cfg_write = ecfg_write & (dstaddr_in[RFAW+1:2]==`ERX_CFG);
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assign rx_offset_write = ecfg_write & (dstaddr_in[RFAW+1:2]==`ERX_OFFSET);
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assign rx_idelay0_write = ecfg_write & (dstaddr_in[RFAW+1:2]==`ERX_IDELAY0);
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assign rx_idelay1_write = ecfg_write & (dstaddr_in[RFAW+1:2]==`ERX_IDELAY1);
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assign rx_testdata_write = ecfg_write & (dstaddr_in[RFAW+1:2]==`ERX_TESTDATA);
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assign rx_status_write = ecfg_write & (dstaddr_in[RFAW+1:2]==`ERX_STATUS);
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//###########################
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//# RXCFG
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//###########################
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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rx_cfg_reg[31:0] <= 'b0;
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else if (rx_cfg_write)
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rx_cfg_reg[31:0] <= data_in[31:0];
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assign test_mode = rx_cfg_reg[0];
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assign mmu_enable = rx_cfg_reg[1];
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assign remap_mode[1:0] = rx_cfg_reg[3:2];
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assign remap_sel[11:0] = rx_cfg_reg[15:4];
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assign remap_pattern[11:0] = rx_cfg_reg[27:16];
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assign mailbox_irq_en = rx_cfg_reg[28];
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//###########################1
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//# STATUS
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//###########################
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always @ (posedge clk)
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if (rx_status_write)
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rx_status_reg[15:0] <= data_in[15:0];
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else
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rx_status_reg[15:0] <= rx_status_reg[15:0] | rx_status[15:0];
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//###########################
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//# GPIO-DATAIN
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//###########################
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always @ (posedge clk)
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rx_gpio_reg[8:0] <= gpio_datain[8:0];
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//###########################1
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//# DYNAMIC REMAP BASE
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//###########################
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always @ (posedge clk)
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if (rx_offset_write)
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rx_offset_reg[31:0] <= data_in[31:0];
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assign remap_base[31:0] = rx_offset_reg[31:0];
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//###########################1
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//# IDELAY TAP VALUES
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//###########################
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always @ (posedge clk)
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if (rx_idelay0_write)
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idelay[31:0] <= data_in[31:0];
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else if(rx_idelay1_write)
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idelay[44:32] <= data_in[12:0];
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//Construct delay for io (5*9 bits)
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assign idelay_value[44:0] = {idelay[44],idelay[35:32],//frame
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idelay[43],idelay[31:28],//d7
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idelay[42],idelay[27:24],//d6
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idelay[41],idelay[23:20],//d5
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idelay[40],idelay[19:16],//d4
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idelay[39],idelay[15:12],//d3
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idelay[38],idelay[11:8], //d2
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idelay[37],idelay[7:4], //d1
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idelay[36],idelay[3:0] //d0
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};
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always @ (posedge clk)
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load_taps <= rx_idelay1_write;
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//###############################
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//# TESTMODE (ADD OR/LFSR..)
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//###############################
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always @ (posedge clk)
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if(rx_testdata_write)
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rx_testdata_reg[31:0] <= data_in[31:0];
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else if(erx_access)
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rx_testdata_reg[31:0] <= rx_testdata_reg[31:0] + erx_packet[71:40];
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//###############################
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//# DATA READBACK MUX
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//###############################
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always @ (posedge clk)
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if(ecfg_read)
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case(dstaddr_in[RFAW+1:2])
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`ERX_CFG: cfg_rdata[31:0] <= {rx_cfg_reg[31:0]};
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`ERX_GPIO: cfg_rdata[31:0] <= {23'b0, rx_gpio_reg[8:0]};
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`ERX_STATUS: cfg_rdata[31:0] <= {16'b0, rx_status_reg[15:0]};
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`ERX_OFFSET: cfg_rdata[31:0] <= {rx_offset_reg[31:0]};
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`ERX_TESTDATA: cfg_rdata[31:0] <= {rx_testdata_reg[31:0]};
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default: cfg_rdata[31:0] <= 32'd0;
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endcase // case (dstaddr_in[RFAW+1:2])
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else
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cfg_rdata[31:0] <= 32'd0;
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//###############################
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//# FORWARD PACKET TO OUTPUT
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//###############################
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//pipeline
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always @ (posedge clk)
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begin
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ecfg_access <= ecfg_read | ecfg_tx_read;
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datamode_out[1:0] <= datamode_in[1:0];
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ctrlmode_out[4:0] <= ctrlmode_in[3:0];
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write_out <= 1'b1;
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dstaddr_out[31:0] <= ecfg_read ? srcaddr_in[31:0] : dstaddr_in[31:0];
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data_out[31:0] <= data_in[31:0];
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srcaddr_out[31:0] <= srcaddr_in[31:0];
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rx_sel <= ~ecfg_read;
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dma_sel <= dma_access;
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mailbox_sel <= mailbox_access;
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tx_sel <= ecfg_tx_read;
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end
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//readback mux (should be one hot!)
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oh_mux4 #(.DW(32))
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mux4(.out (data_mux[31:0]),
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.in0 (cfg_rdata[31:0]), .sel0 (rx_sel),
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.in1 (mailbox_rdata[31:0]),.sel1 (mailbox_sel),
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.in2 (edma_rdata[31:0]), .sel2 (dma_sel),
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.in3 (data_out[31:0]), .sel3 (tx_sel)
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);
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emesh2packet #(.AW(AW))
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e2p (.packet_out (ecfg_packet[PW-1:0]),
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.data_out (data_mux[31:0]),
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/*AUTOINST*/
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// Inputs
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.write_out (write_out),
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.datamode_out (datamode_out[1:0]),
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.ctrlmode_out (ctrlmode_out[4:0]),
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.dstaddr_out (dstaddr_out[AW-1:0]),
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.srcaddr_out (srcaddr_out[AW-1:0]));
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endmodule // ecfg_rx
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// Local Variables:
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// verilog-library-directories:("." "../../emesh/hdl" "../../common/hdl")
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// End:
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