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236 lines
7.7 KiB
Verilog
236 lines
7.7 KiB
Verilog
module etx_core(/*AUTOARG*/
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// Outputs
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tx_data_slow, tx_frame_slow, txrd_wait, txrr_wait, txwr_wait,
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etx_cfg_access, etx_cfg_packet,
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// Inputs
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nreset, clk, tx_rd_wait, tx_wr_wait, txrd_access, txrd_packet,
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txrd_full, txrr_access, txrr_packet, txrr_full, txwr_access,
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txwr_packet, txwr_full, etx_cfg_wait
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);
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parameter AW = 32;
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parameter DW = 32;
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parameter PW = 104;
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parameter RFAW = 6;
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parameter ID = 12'h999;
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//Clocks,reset,config
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input nreset;
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input clk;
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//IO interface
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output [63:0] tx_data_slow;
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output [3:0] tx_frame_slow;
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input tx_rd_wait;
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input tx_wr_wait;
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//TXRD
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input txrd_access;
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input [PW-1:0] txrd_packet;
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output txrd_wait;
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input txrd_full;//sysclk domain
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//TXRR
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input txrr_access;
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input [PW-1:0] txrr_packet;
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output txrr_wait;
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input txrr_full;//sysclk domain
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//TXWR
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input txwr_access;
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input [PW-1:0] txwr_packet;
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output txwr_wait;
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input txwr_full; //sysclk domain
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//Configuration Interface (for ERX)
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output etx_cfg_access;
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output [PW-1:0] etx_cfg_packet;
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input etx_cfg_wait;
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//for status?
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wire[15:0] tx_status;
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// End of automatics
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire burst_enable; // From etx_cfg of etx_cfg.v
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wire cfg_access; // From etx_arbiter of etx_arbiter.v
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wire [3:0] ctrlmode; // From etx_cfg of etx_cfg.v
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wire ctrlmode_bypass; // From etx_cfg of etx_cfg.v
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wire emmu_access; // From etx_mmu of emmu.v
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wire [PW-1:0] emmu_packet; // From etx_mmu of emmu.v
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wire etx_access; // From etx_arbiter of etx_arbiter.v
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wire [PW-1:0] etx_packet; // From etx_arbiter of etx_arbiter.v
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wire etx_rd_wait; // From etx_protocol of etx_protocol.v
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wire etx_remap_access; // From etx_remap of etx_remap.v
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wire [PW-1:0] etx_remap_packet; // From etx_remap of etx_remap.v
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wire etx_wait; // From etx_protocol of etx_protocol.v
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wire etx_wr_wait; // From etx_protocol of etx_protocol.v
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wire [8:0] gpio_data; // From etx_cfg of etx_cfg.v
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wire gpio_enable; // From etx_cfg of etx_cfg.v
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wire mmu_enable; // From etx_cfg of etx_cfg.v
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wire remap_enable; // From etx_cfg of etx_cfg.v
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wire tx_access; // From etx_protocol of etx_protocol.v
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wire tx_burst; // From etx_protocol of etx_protocol.v
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wire tx_enable; // From etx_cfg of etx_cfg.v
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// End of automatics
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//##################################################################
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//# ARBITER (SELECT BETWEEN TX, RX, RR)
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//##################################################################
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etx_arbiter #(.ID(ID))
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etx_arbiter (
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/*AUTOINST*/
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// Outputs
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.txwr_wait (txwr_wait),
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.txrd_wait (txrd_wait),
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.txrr_wait (txrr_wait),
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.etx_access (etx_access),
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.cfg_access (cfg_access),
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.etx_packet (etx_packet[PW-1:0]),
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// Inputs
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.clk (clk),
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.nreset (nreset),
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.txwr_access (txwr_access),
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.txwr_packet (txwr_packet[PW-1:0]),
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.txrd_access (txrd_access),
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.txrd_packet (txrd_packet[PW-1:0]),
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.txrr_access (txrr_access),
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.txrr_packet (txrr_packet[PW-1:0]),
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.etx_wait (etx_wait),
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.etx_cfg_wait (etx_cfg_wait));
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//##################################################################
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//# REMAPPING DESTINATION ADDRESS
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//##################################################################
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/*etx_remap AUTO_TEMPLATE (
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.emesh_\(.*\)_in (etx_\1[]),
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.emesh_\(.*\)_out (etx_remap_\1[]),
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.remap_en (remap_enable),
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);
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*/
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etx_remap etx_remap (
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/*AUTOINST*/
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// Outputs
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.emesh_access_out(etx_remap_access), // Templated
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.emesh_packet_out(etx_remap_packet[PW-1:0]), // Templated
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// Inputs
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.clk (clk),
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.nreset (nreset),
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.emesh_access_in(etx_access), // Templated
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.emesh_packet_in(etx_packet[PW-1:0]), // Templated
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.remap_en (remap_enable), // Templated
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.etx_wait (etx_wait));
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//##################################################################
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//# TABLE LOOKUP ADDRESS TRANSLATION
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//##################################################################
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/*emmu AUTO_TEMPLATE (.reg_access (etx_cfg_access),
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.reg_packet (etx_packet[PW-1:0]),
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.emesh_\(.*\)_in (etx_remap_\1[]),
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.emesh_\(.*\)_out (emmu_\1[]),
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.mmu_en (mmu_enable),
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.\(.*\)_clk (clk),
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.emesh_wait_in (etx_wait),
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);
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*/
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emmu etx_mmu (.reg_rdata (), // not used (no readback from MMU)
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/*AUTOINST*/
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// Outputs
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.emesh_access_out (emmu_access), // Templated
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.emesh_packet_out (emmu_packet[PW-1:0]), // Templated
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// Inputs
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.wr_clk (clk), // Templated
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.rd_clk (clk), // Templated
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.nreset (nreset),
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.mmu_en (mmu_enable), // Templated
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.reg_access (etx_cfg_access), // Templated
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.reg_packet (etx_packet[PW-1:0]), // Templated
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.emesh_access_in (etx_remap_access), // Templated
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.emesh_packet_in (etx_remap_packet[PW-1:0]), // Templated
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.emesh_wait_in (etx_wait)); // Templated
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//##################################################################
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//# ELINK PROTOCOL CONVERTER (104 bit-->64 bits)
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//##################################################################
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/*etx_protocol AUTO_TEMPLATE (
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.etx_rd_wait (etx_rd_wait),
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.etx_wr_wait (etx_wr_wait),
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.etx_wait (etx_wait),
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.etx_\(.*\) (emmu_\1[]),
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);
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*/
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etx_protocol #(.ID(ID))
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etx_protocol (
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/*AUTOINST*/
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// Outputs
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.etx_rd_wait (etx_rd_wait), // Templated
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.etx_wr_wait (etx_wr_wait), // Templated
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.etx_wait (etx_wait), // Templated
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.tx_burst (tx_burst),
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.tx_access (tx_access),
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.tx_data_slow (tx_data_slow[63:0]),
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.tx_frame_slow (tx_frame_slow[3:0]),
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// Inputs
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.nreset (nreset),
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.clk (clk),
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.etx_access (emmu_access), // Templated
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.etx_packet (emmu_packet[PW-1:0]), // Templated
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.tx_enable (tx_enable),
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.burst_enable (burst_enable),
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.gpio_data (gpio_data[8:0]),
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.gpio_enable (gpio_enable),
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.ctrlmode_bypass (ctrlmode_bypass),
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.ctrlmode (ctrlmode[3:0]),
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.tx_rd_wait (tx_rd_wait),
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.tx_wr_wait (tx_wr_wait));
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//##################################################################
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//# TX CONFIGURATION
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//##################################################################
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etx_cfg etx_cfg (.tx_status ({7'b0,
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tx_burst,
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tx_rd_wait,
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tx_wr_wait,
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txrr_wait,
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txrd_wait,
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txwr_wait,
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txrr_full,
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txrd_full,
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txwr_full
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}),
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/*AUTOINST*/
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// Outputs
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.etx_cfg_access (etx_cfg_access),
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.etx_cfg_packet (etx_cfg_packet[PW-1:0]),
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.tx_enable (tx_enable),
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.mmu_enable (mmu_enable),
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.gpio_enable (gpio_enable),
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.remap_enable (remap_enable),
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.burst_enable (burst_enable),
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.gpio_data (gpio_data[8:0]),
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.ctrlmode (ctrlmode[3:0]),
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.ctrlmode_bypass (ctrlmode_bypass),
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// Inputs
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.nreset (nreset),
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.clk (clk),
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.cfg_access (cfg_access),
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.etx_access (etx_access),
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.etx_packet (etx_packet[PW-1:0]),
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.etx_wait (etx_wait));
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endmodule // elink
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// Local Variables:
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// verilog-library-directories:("." "../../emmu/hdl" "../../memory/hdl" "../../common/hdl")
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// End:
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