mirror of
https://github.com/aolofsson/oh.git
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220 lines
6.9 KiB
Coq
220 lines
6.9 KiB
Coq
/*
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===============================================================
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8 bit to 10 bit Encoder
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===============================================================
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*/
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// File Name: oh_8b10b_encode.v
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// Version: 1.0v
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//
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// Author: Prasad Pandit
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// Contact: prasadp4009@gmail.com/prasad@pdx.edu
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//
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// Date created: 03/19/2016
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// Date modified: 03/19/2016
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//
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// Text-editor used: Gvim 7v4 & NPP
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//
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// ************************************************************
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module oh_8b10b_encode(
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input clk,
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input nreset,
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input ksel,
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input [7:0] data_in,
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input disp_in,
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output RD_out,
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output [9:0] data_out
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);
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reg ksel_latch;
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reg disparity_latch;
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reg [7:0] data_in_latch;
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reg [9:0] data_out_latch;
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reg RD_latch;
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wire [9:0] data_out_wire;
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wire disparity;
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wire [7:0] TXD;
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wire K;
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wire [9:0] code_group;
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//----------------Signals to be used-----------
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wire [4:0] TXD_5;
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wire [2:0] TXD_3;
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wire A,B,C,D,E,F,G,H;
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wire a,b,c,d,e,i_rdp,i_rdn,f,g,h,j;
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wire NA,NB,NC,ND,NE;
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wire [2:0] bit6_disp;
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wire [2:0] bit4_disp;
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wire [5:0] code_6b;
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wire [3:0] code_4b;
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wire bit_6rd;
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wire bit_4rd;
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wire invert_6;
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wire invert_4;
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wire invert_3b4;
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wire spe_4bp, spe_4bn;
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wire k_j;
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wire k_i;
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assign RD_out = RD_latch;
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assign data_out = data_out_latch;
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assign TXD = data_in_latch;
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assign K = ksel_latch;
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assign disparity = disparity_latch;
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assign data_out_wire = code_group;
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//----------------------------------------------
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//---------------Code Group Output--------------
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assign code_group = {code_6b,code_4b};
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//----------------------------------------------
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//---------------TXD to 5 bit and 3 bit---------
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assign TXD_5 = TXD[4:0];
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assign TXD_3 = TXD[7:5];
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//----------------------------------------------
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//----------------Special Code Group Logic----------------------------------------------------------------------------------------------------------
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assign k_i = (TXD[4:0] == 5'b11100);
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assign k_j = (TXD[7:5] == 3'b111);
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//----------------------------------------------
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assign invert_6 = ((TXD_5 == 'd0) | (TXD_5 == 'd1) | (TXD_5 == 'd2) | (TXD_5 == 'd4) | (TXD_5 == 'd7) | (TXD_5 == 'd8)
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| (TXD_5 == 'd15) | (TXD_5 == 'd16) | (TXD_5 == 'd23) | (TXD_5 == 'd24) | (TXD_5 == 'd27) |
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(TXD_5 == 'd29) | (TXD_5 == 'd30) | (TXD_5 == 'd31));
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assign invert_4 = ((TXD_3 == 'd0) | (TXD_3 == 'd3) | (TXD_3 == 'd4) | (TXD_3 == 'd7));
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assign invert_3b4 = ((TXD_5 == 'd0) | (TXD_5 == 'd1) | (TXD_5 == 'd2) | (TXD_5 == 'd4) | (TXD_5 == 'd8) |
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(TXD_5 == 'd15) | (TXD_5 == 'd16) | (TXD_5 == 'd23) | (TXD_5 == 'd24) | (TXD_5 == 'd27) |
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(TXD_5 == 'd29) | (TXD_5 == 'd30) | (TXD_5 == 'd31));// | (K & TXD_5 ==k_i & ~disparity);
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assign spe_4bp = ((TXD == 'hEB) | (TXD == 'hED) | (TXD == 'hEE));
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assign spe_4bn = ((TXD == 'hF1) | (TXD == 'hF2) | (TXD == 'hF4));
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assign bit6_disp = (code_6b[5] + code_6b[4] + code_6b[3] + code_6b[2] + code_6b[1] + code_6b[0]);
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assign bit4_disp = (code_4b[3] + code_4b[2] + code_4b[1] + code_4b[0]);
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assign bit_6rd = (bit6_disp > 'd3) & (bit6_disp != 'd3);
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assign bit_4rd = (bit4_disp > 'd2) & (bit4_disp != 'd2);
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assign RD = (bit6_disp == 'd3 & bit4_disp == 'd2) ? disparity : ((bit4_disp == 'd2) ? bit_6rd : bit_4rd);
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assign code_6b[5] = K ? (disparity ? NA : A ):
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((disparity & invert_6) ? ~a : a);
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assign code_6b[4] = K ? (disparity ? NB : B) :
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((disparity & invert_6) ? ~b : b);
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assign code_6b[3] = K ? (disparity ? NC : C) :
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((disparity & invert_6) ? ~c : c);
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assign code_6b[2] = K ? (disparity ? ND : D) :
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((disparity & invert_6) ? ~d : d);
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assign code_6b[1] = K ? (disparity ? NE : E) :
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((disparity & invert_6) ? ~e : e);
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assign code_6b[0] = K ? (disparity ? ~k_i : k_i) :
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((disparity & invert_6) ? i_rdp: i_rdn);
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assign code_4b[3] = (disparity) ? ((k_j & K) ? 'b0 : (K ? ~f : (spe_4bp ? 'b1 : ((invert_4) ? (invert_3b4 ? ~f : f): f)))) :
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((k_j & K) ? 'b1 : (K ? f :(spe_4bn ? 'b0 :((invert_4) ? (invert_3b4 ? f : ~f) : f))));
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assign code_4b[2] = (disparity) ? ((k_j & K) ? 'b1 : (K ? ~g :(spe_4bp ? 'b0 : ((invert_4) ? (invert_3b4 ? ~g : g) : g)))) :
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((k_j & K) ? 'b0 : (K ? g :(spe_4bn ? 'b1 :((invert_4) ? (invert_3b4 ? g : ~g) : g))));
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assign code_4b[1] = (disparity) ? ((k_j & K) ? 'b1 : (K ? ~h :(spe_4bp ? 'b0 : ((invert_4) ? (invert_3b4? ~h : h) : h)))) :
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((k_j & K) ? 'b0 : (K ? h :(spe_4bn ? 'b1 :((invert_4) ? (invert_3b4 ? h : ~h) : h))));
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assign code_4b[0] = (disparity) ? ((k_j & K) ? 'b1 : (K ? ~j :(spe_4bp ? 'b0 : ((invert_4) ? (invert_3b4 ? ~j : j): j)))) :
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((k_j & K) ? 'b0 : (K ? j :(spe_4bn ? 'b1 :((invert_4) ? (invert_3b4 ? j : ~j) : j))));
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assign A = TXD[0];
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assign B = TXD[1];
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assign C = TXD[2];
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assign D = TXD[3];
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assign E = TXD[4];
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assign F = TXD[5];
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assign G = TXD[6];
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assign H = TXD[7];
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assign NA = ~A;
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assign NB = ~B;
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assign NC = ~C;
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assign ND = ~D;
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assign NE = ~E;
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assign NF = ~F;
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assign NG = ~G;
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assign NH = ~H;
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//----------------Data Code Group Logic----------------------------------------------------------------------------------------------------------
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assign a = (E & A) | (NE & ND & NB & NA) | (NE & D & NB & A) | (NE & ND & B & A) | (NE & ND & NC & B)
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| (C & NB & A) | (NC & B & A) | (NC & NB & D);
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assign b = (E & B & NA) | (ND & B & A)| (NE & D & B) |(D & NC & B)
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|(NE & C & B) |(NE & ND & C & NA) |(NE & ND & NC & A) |(NC & NB & NA & D) |(NC & NB & NA & E) ;
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assign c = (NE & ND & B & NA) | (NE & ND & NB & A) |
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(NE & D & NB & NA) | (E & ND & NB & NA) | (NE & ND & C & B) | (E & C & B) | (C & NB & A) | (E & C & NB) | (C & B & NA);
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assign d = (NE & ND & NB & NA) | (NE & ND & NC & NB) | (NE & NC & B & NA) | (D & NB & A) | (D & B & NA)
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| (NE & D & B) | (E & D & NC & B) | (D & C & NB & NA);
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assign e = E | (ND & NC & NB & NA) | (D & C & B & A);
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assign i_rdn = (NE & NB & NA) | (ND & NB & NA) | (NE & ND & B & NA) | (NE & ND & NB) | (D & C & B & A)
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| (ND & NC & NA) | (E & ND & NC & NB) | (NE & NC & NB & A) | (NC & NB & NA) | (NE & ND & NC) | (NE & NC & B & NA);
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assign i_rdp = (NE & ND & ((B & A) | (C & B) | (C & A))) | (NC & B & NA & (E ^ D)) | (E & D & C & (B ^ A)) | (E & ND & C & ((B & A) | (NB & NA)))
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| (NE & D & NC & NB & A) | (E & D & NC & B & A) | (E & ND & NC & NB & A) | (NE & D & C & NB & NA);
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assign f = (NG & F);
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assign g = (NF & (NH | G));
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assign h = (H & (NG | NF)) | (NH & G & F);
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assign j = (NH & (F | G)) | (G & F);
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//----------------------------------------------------------------------X-------------------------------------------------------------------------
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always@(posedge clk or negedge nreset)
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begin
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if(~nreset)
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begin
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ksel_latch <= 1'd0;
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disparity_latch <= 1'd0;
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data_in_latch <= 8'd0;
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RD_latch <= 1'd0;
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data_out_latch <= 10'd0;
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end
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else
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begin
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ksel_latch <= ksel;
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data_in_latch <= data_in;
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disparity_latch <= disp_in;
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RD_latch <= RD;
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data_out_latch <= data_out_wire;
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end
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end
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endmodule
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