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145 lines
4.5 KiB
Verilog
145 lines
4.5 KiB
Verilog
//#############################################################################
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//# Purpose: Clock divider with 2 outputs #
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// Secondary clock must be multiple of first clock #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_clockdiv
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(
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//inputs
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input clk, // main clock
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input nreset, // async active low reset (from oh_rsync)
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input clkchange, // indicates a parameter change
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input clken, // clock enable
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input [7:0] clkdiv, // [7:0]=period (0==bypass, 1=div/2, 2=div/3, etc)
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input [15:0] clkphase0, // [7:0]=rising,[15:8]=falling
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input [15:0] clkphase1, // [7:0]=rising,[15:8]=falling
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//outputs
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output clkout0, // primary output clock
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output clkrise0, // rising edge match
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output clkfall0, // falling edge match
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output clkout1, // secondary output clock
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output clkrise1, // rising edge match
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output clkfall1, // falling edge match
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output clkstable // clock is guaranteed to be stable
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);
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//regs
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reg [7:0] counter;
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reg clkout0_reg;
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reg clkout1_reg;
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reg clkout1_shift;
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reg [2:0] period;
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wire period_match;
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wire [3:0] clk1_sel;
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wire [3:0] clk1_sel_sh;
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wire [1:0] clk0_sel;
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wire [1:0] clk0_sel_sh;
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//###########################################
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//# CHANGE DETECT (count 8 periods)
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//###########################################
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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period[2:0] <= 'b0;
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else if (clkchange)
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period[2:0] <='b0;
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else if(period_match & ~clkstable)
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period[2:0] <= period[2:0] +1'b1;
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assign clkstable = (period[2:0]==3'b111);
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//###########################################
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//# CYCLE COUNTER
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//###########################################
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always @ (posedge clk or negedge nreset)
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if (!nreset)
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counter[7:0] <= 'b0;
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else if(clken)
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if(period_match)
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counter[7:0] <= 'b0;
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else
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counter[7:0] <= counter[7:0] + 1'b1;
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assign period_match = (counter[7:0]==clkdiv[7:0]);
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//###########################################
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//# RISING/FALLING EDGE SELECTORS
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//###########################################
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assign clkrise0 = (counter[7:0]==clkphase0[7:0]);
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assign clkfall0 = (counter[7:0]==clkphase0[15:8]);
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assign clkrise1 = (counter[7:0]==clkphase1[7:0]);
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assign clkfall1 = (counter[7:0]==clkphase1[15:8]);
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//###########################################
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//# CLKOUT0
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//###########################################
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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clkout0_reg <= 1'b0;
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else if(clkrise0)
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clkout0_reg <= 1'b1;
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else if(clkfall0)
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clkout0_reg <= 1'b0;
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// clock mux
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assign clk0_sel[1] = (clkdiv[7:0]==8'd0); // not implemented
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assign clk0_sel[0] = ~(clkdiv[7:0]==8'd0);
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// clock select needs to be stable high
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oh_lat0 #(.DW(2))
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latch_clk0 (.out (clk0_sel_sh[1:0]),
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.clk (clk),
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.in (clk0_sel[1:0]));
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oh_clockmux #(.N(2))
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mux_clk0 (.clkout(clkout0),
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.en(clk0_sel[1:0]),
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.clkin({clk, clkout0_reg}));
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//###########################################
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//# CLKOUT1
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//###########################################
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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clkout1_reg <= 1'b0;
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else if(clkrise1)
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clkout1_reg <= 1'b1;
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else if(clkfall1)
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clkout1_reg <= 1'b0;
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// creating divide by 2 shifted clock with negedge
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always @ (negedge clk)
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clkout1_shift <= clkout1_reg;
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// clock mux
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assign clk1_sel[3] = 1'b0; // not implemented
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assign clk1_sel[2] = (clkdiv[7:0]==8'd0); // div1 (bypass)
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assign clk1_sel[1] = (clkdiv[7:0]==8'd1); // div2 clock
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assign clk1_sel[0] = |clkdiv[7:1]; // all others
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// clock select needs to be stable high
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oh_lat0 #(.DW(4))
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latch_clk1 (.out (clk1_sel_sh[3:0]),
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.clk (clk),
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.in (clk1_sel[3:0]));
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oh_clockmux #(.N(4))
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mux_clk1 (.clkout(clkout1),
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.en(clk1_sel[3:0]),
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.clkin({1'b0, clk, clkout1_shift, clkout1_reg}));
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endmodule // oh_clockdiv
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