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74 lines
1.8 KiB
Verilog
74 lines
1.8 KiB
Verilog
//#############################################################################
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//# Function: Binary to gray encoder #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_counter #(parameter DW = 32, // width of data inputs
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parameter TYPE = "INCREMENT" // also DECREMENT, GRAY, LFSR
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)
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(
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input clk, // clk input
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input in, // input to count
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input en, // enable counter
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input load, // load counter
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input [DW-1:0] load_data,// load data
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output [DW-1:0] count, // current count value
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output carry, // carry out from counter
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output zero // counter is zero
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);
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// local variables
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reg [DW-1:0] count;
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reg carry;
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wire [DW-1:0] count_in;
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wire carry_in;
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// configure counter based on type
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generate
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if(TYPE=="INCREMENT")
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begin
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assign {carry_in,count_in[DW-1:0]} = count[DW-1:0] + in;
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end
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else if(TYPE=="DECREMENT")
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begin
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assign count_in[DW-1:0] = count[DW-1:0] + in;
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end
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else if (TYPE=="GRAY")
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begin
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initial
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$display ("NOT IMPLEMENTED");
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end
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else if (TYPE=="LFSR")
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begin
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initial
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$display ("NOT IMPLEMENTED");
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end
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endgenerate
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// counter
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always @(posedge clk)
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if(load)
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begin
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carry <= 1'b0;
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count[DW-1:0] <= load_data[DW-1:0];
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end
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else if (en)
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begin
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carry <= carry_in;
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count[DW-1:0] <= count_in[DW-1:0];
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end
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// counter expired
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assign zero = ~(count[DW-1:0]);
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endmodule // oh_counter
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