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61 lines
1.7 KiB
Verilog
61 lines
1.7 KiB
Verilog
//#############################################################################
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//# Function: Carry Save Adder (4:2) #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_csa42 #( parameter DW = 1 // data width
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)
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( input [DW-1:0] in0, //input
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input [DW-1:0] in1,//input
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input [DW-1:0] in2,//input
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input [DW-1:0] in3,//input
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input [DW-1:0] cin,//carry in
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output [DW-1:0] s, //sum
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output [DW-1:0] c, //carry
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output [DW-1:0] cout //carry out
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);
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localparam ASIC = `CFG_ASIC; // use asic library
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generate
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if(ASIC)
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begin
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asic_csa42 i_csa42[DW-1:0] (.s(s[DW-1:0]),
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.cout(cout[DW-1:0]),
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.c(c[DW-1:0]),
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.cin(cin[DW-1:0]),
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.in3(in3[DW-1:0]),
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.in2(in2[DW-1:0]),
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.in1(in1[DW-1:0]),
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.in0(in0[DW-1:0]));
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end
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else
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begin
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wire [DW-1:0] s_int;
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assign s[DW-1:0] = in0[DW-1:0] ^
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in1[DW-1:0] ^
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in2[DW-1:0] ^
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in3[DW-1:0] ^
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cin[DW-1:0];
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assign s_int[DW-1:0] = in1[DW-1:0] ^
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in2[DW-1:0] ^
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in3[DW-1:0];
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assign c[DW-1:0] = (in0[DW-1:0] & s_int[DW-1:0]) |
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(in0[DW-1:0] & cin[DW-1:0]) |
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(s_int[DW-1:0] & cin[DW-1:0]);
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assign cout[DW-1:0] = (in1[DW-1:0] & in2[DW-1:0]) |
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(in1[DW-1:0] & in3[DW-1:0]) |
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(in2[DW-1:0] & in3[DW-1:0]);
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end // else: !if(ASIC)
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endgenerate
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endmodule // oh_csa42
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