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53 lines
1.6 KiB
Verilog
53 lines
1.6 KiB
Verilog
//CSA6:2 Compressor
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//#############################################################################
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//# Function: Carry Save Adder (6:2) #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_csa62 #(parameter DW = 1 // data width
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)
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( input [DW-1:0] in0, //input
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input [DW-1:0] in1,//input
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input [DW-1:0] in2,//input
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input [DW-1:0] in3,//input
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input [DW-1:0] in4,//input
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input [DW-1:0] in5,//input
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input [DW-1:0] cin0,//carry in
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input [DW-1:0] cin1,//carry in
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input [DW-1:0] cin2,//carry in
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output [DW-1:0] s, //sum
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output [DW-1:0] c, //carry
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output [DW-1:0] cout0, //carry out
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output [DW-1:0] cout1, //carry out
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output [DW-1:0] cout2 //carry out
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);
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wire [DW-1:0] s_int0;
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wire [DW-1:0] s_int1;
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oh_csa32 #(.DW(DW)) csa32_0 (.in0(in0[DW-1:0]),
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.in1(in1[DW-1:0]),
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.in2(in2[DW-1:0]),
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.c(cout0[DW-1:0]),
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.s(s_int0[DW-1:0]));
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oh_csa32 #(.DW(DW)) csa32_1 (.in0(in3[DW-1:0]),
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.in1(in4[DW-1:0]),
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.in2(in5[DW-1:0]),
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.c(cout1[DW-1:0]),
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.s(s_int1[DW-1:0]));
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oh_csa42 #(.DW(DW)) csa42 (.in0(s_int0[DW-1:0]),
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.in1(s_int1[DW-1:0]),
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.in2(cin0[DW-1:0]),
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.in3(cin1[DW-1:0]),
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.cin(cin2[DW-1:0]),
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.cout(cout2[DW-1:0]),
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.c(c[DW-1:0]),
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.s(s[DW-1:0]));
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endmodule // oh_csa62
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