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51 lines
1.5 KiB
Verilog
51 lines
1.5 KiB
Verilog
//#############################################################################
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//# Function: Clock domain one cycle pulse transfer #
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// !!"din" pulse width must be 2x greater than clkout width!!! #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_pulse2pulse (
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input nrstin, //input domain reset
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input din, //input pulse (one clock cycle)
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input clkin, //input clock
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input nrstout, //output domain reset
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input clkout, //output clock
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output dout //output pulse (one clock cycle)
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);
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// local wires
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reg toggle_reg;
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reg pulse_reg;
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wire toggle;
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//pulse to toggle
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assign toggle = din ? ~toggle_reg : toggle_reg;
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always @ (posedge clkin)
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if(~nrstin)
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toggle_reg <= 1'b0;
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else
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toggle_reg <= toggle;
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//metastability synchronizer
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oh_dsync sync(.dout (toggle_sync),
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.din (toggle),
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.nreset (nrstout),
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.clk (clkout));
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//toogle to pulse
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always @ (posedge clkout)
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if(!nrstout)
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pulse_reg <= 1'b0;
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else
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pulse_reg <= toggle_sync;
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assign dout = pulse_reg ^ toggle_sync;
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endmodule // oh_pulse2pulse
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