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30 lines
968 B
Verilog
30 lines
968 B
Verilog
//#############################################################################
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//# Function: Power supply header switch #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_pwr_gate (
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input npower, // active low power on
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input vdd, // input supply
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output vddg // gated output supply
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);
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localparam ASIC = `CFG_ASIC; // use asic library
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`ifdef TARGET_SIM
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assign vddg = ((vdd===1'b1) && (npower===1'b0)) ? 1'b1 : 1'bX;
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`else
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generate
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if(ASIC)
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begin : asic
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asic_pwr_header i_header (.npower(npower),
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.vdd(vdd),
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.vddg(vddg));
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end
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endgenerate
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`endif
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endmodule // oh_pwr_gate
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