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39 lines
1.1 KiB
Verilog
39 lines
1.1 KiB
Verilog
//#############################################################################
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//# Function: Reset synchronizer (async assert, sync deassert) #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_rsync #(parameter PS = 2 // number of sync stages
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)
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(
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input clk,
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input nrst_in,
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output nrst_out
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);
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localparam ASIC = `CFG_ASIC; // use ASIC lib
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generate
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if(ASIC)
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begin : g0
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asic_rsync asic_rsync (.clk(clk),
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.nrst_in(nrst_in),
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.nrst_out(nrst_out));
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end
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else
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begin :g0
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reg [PS-1:0] sync_pipe;
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always @ (posedge clk or negedge nrst_in)
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if(!nrst_in)
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sync_pipe[PS-1:0] <= 1'b0;
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else
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sync_pipe[PS-1:0] <= {sync_pipe[PS-2:0],1'b1};
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assign nrst_out = sync_pipe[PS-1];
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end
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endgenerate
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endmodule // oh_rsync
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