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27 lines
970 B
Verilog
27 lines
970 B
Verilog
//#############################################################################
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//# Function: Bidirectional port with output-enable #
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//#############################################################################
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//# Author: Ola Jeppsson #
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//# SPDX-License-Identifier: MIT #
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//#############################################################################
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module oh_tristate #(parameter N = 1) // width of port
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(
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inout [N-1:0] io, // bidirectional port
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input [N-1:0] oe, // output enable (1 = output, 0 = input)
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output [N-1:0] in, // port as input
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input [N-1:0] out // port as output
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);
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assign in[N-1:0] = io[N-1:0];
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genvar i;
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generate
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for (i = 0; i < N; i = i + 1)
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begin : gen_oh_tristate
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assign io[i] = oe[i] ? out[i] : 1'bZ;
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end
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endgenerate
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endmodule // oh_tristate
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