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d275406aa6
- holding rx in reset state until tx is done - removing reset from all pipeline registers - removing reset from oddr/iddr - the idea is to keep things quiet not to block in lots of places. The only real block needed is in the FIFO to keep "noise" from propagating past the link. The link should be kept in a safe reset state until the rx fram is stable and the clock is running so that the pipe can be cleaned out.
83 lines
2.3 KiB
Verilog
83 lines
2.3 KiB
Verilog
module erx_remap (/*AUTOARG*/
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// Outputs
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emesh_access_out, emesh_packet_out,
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// Inputs
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clk, emesh_access_in, emesh_packet_in, remap_mode, remap_sel,
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remap_pattern, remap_base
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);
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parameter AW = 32;
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parameter DW = 32;
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parameter PW = 104;
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parameter ID = 12'h808;
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//Clock/reset
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input clk;
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//Input from arbiter
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input emesh_access_in;
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input [PW-1:0] emesh_packet_in;
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//Configuration
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input [1:0] remap_mode; //00=none,01=static,02=continuity
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input [11:0] remap_sel; //number of bits to remap
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input [11:0] remap_pattern; //static pattern to map to
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input [31:0] remap_base; //remap offset
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//Output to TX IO
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output emesh_access_out;
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output [PW-1:0] emesh_packet_out;
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wire [31:0] static_remap;
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wire [31:0] dynamic_remap;
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wire [31:0] remap_mux;
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wire write_in;
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wire read_in;
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wire [31:0] addr_in;
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wire [31:0] addr_out;
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wire remap_en;
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reg emesh_access_out;
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reg [PW-1:0] emesh_packet_out;
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//TODO:FIX!??
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parameter[5:0] colid = ID[5:0];
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//parsing packet
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assign addr_in[31:0] = emesh_packet_in[39:8];
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assign write_in = emesh_packet_in[1];
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assign read_in = ~emesh_packet_in[1];
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//simple static remap
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assign static_remap[31:20] = (remap_sel[11:0] & remap_pattern[11:0]) |
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(~remap_sel[11:0] & addr_in[31:20]);
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assign static_remap[19:0] = addr_in[19:0];
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//more complex compresssed map
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assign dynamic_remap[31:0] = addr_in[31:0] //input
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- (colid << 20) //subtracing elink (start at 0)
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+ remap_base[31:0] //adding back base
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- (addr_in[31:26]<<$clog2(colid));
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//Static, dynamic, or no remap
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assign remap_mux[31:0] = (remap_mode[1:0]==2'b00) ? addr_in[31:0] :
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(remap_mode[1:0]==2'b01) ? static_remap[31:0] :
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dynamic_remap[31:0];
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//Access pipeline
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always @ (posedge clk)
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emesh_access_out <= emesh_access_in;
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//Packet Remapping
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always @ (posedge clk)
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emesh_packet_out[PW-1:0] <= {emesh_packet_in[103:40],
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remap_mux[31:0],
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emesh_packet_in[7:0]
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};
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endmodule // etx_mux
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