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76 lines
1.6 KiB
Verilog
76 lines
1.6 KiB
Verilog
module erx_timer (/*AUTOARG*/
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// Outputs
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timeout,
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// Inputs
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clk, reset, timer_cfg, stop_count, start_count
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);
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parameter DW = 32;
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parameter AW = 32;
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input clk;
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input reset;
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input [1:0] timer_cfg; //masks MSB of each byte (all zero is off)
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input stop_count;
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input start_count;
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output timeout;
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reg [31:0] timeout_reg;
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reg do_count;
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wire timer_en;
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wire start_count_sync;
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//Synchronize the start count
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synchronizer #(.DW(1)) sync(
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// Outputs
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.out (start_count_sync),
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// Inputs
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.in (start_count),
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.clk (clk),
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.reset (reset)
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);
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assign timer_en = |(timer_cfg[1:0]);
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always @ (posedge clk)
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if(reset)
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begin
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do_count <=1'b0;
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timeout_reg[31:0] <= 32'hffffffff;
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end
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else if(start_count_sync & timer_en)
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begin
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do_count <=1'b1;
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timeout_reg[31:0] <= (timer_cfg[1:0]==2'b01) ? 32'h000000ff :
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(timer_cfg[1:0]==2'b10) ? 32'h0000ffff :
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32'hffffffff;
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end
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else if(stop_count)
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begin
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do_count <=1'b0;
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end
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else if(timer_expired)
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begin
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do_count <=1'b0;
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timeout_reg[31:0] <= 32'hffffffff;
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end
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else if(do_count)
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begin
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timeout_reg[31:0] <= timeout_reg[31:0]-1'b1;
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end
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assign timer_expired = ~(|timeout_reg[31:0]);
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assign timeout = timer_en & timer_expired;
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endmodule // erx_timeout
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// Local Variables:
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// verilog-library-directories:("." "../../common/hdl" )
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// End:
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