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71 lines
1.8 KiB
Verilog
71 lines
1.8 KiB
Verilog
/*
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* Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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`timescale 1ns / 1ps
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module test_aes_192;
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// Inputs
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reg clk;
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reg [127:0] state;
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reg [191:0] key;
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// Outputs
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wire [127:0] out;
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// Instantiate the Unit Under Test (UUT)
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aes_192 uut (
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.clk(clk),
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.state(state),
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.key(key),
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.out(out)
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);
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initial begin
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clk = 0;
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state = 0;
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key = 0;
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#100;
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/*
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* TIMEGRP "key" OFFSET = IN 6.4 ns VALID 6 ns AFTER "clk" HIGH;
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* TIMEGRP "state" OFFSET = IN 6.4 ns VALID 6 ns AFTER "clk" HIGH;
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* TIMEGRP "out" OFFSET = OUT 2.2 ns BEFORE "clk" HIGH;
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*/
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@ (negedge clk);
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#2;
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state = 128'h3243f6a8885a308d313198a2e0370734;
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key = 192'h2b7e151628aed2a6abf7158809cf4f3c762e7160f38b4da5;
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#10;
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state = 128'h00112233445566778899aabbccddeeff;
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key = 192'h000102030405060708090a0b0c0d0e0f1011121314151617;
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#10;
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state = 128'h0;
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key = 192'h0;
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#230;
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if (out !== 128'hf9fb29aefc384a250340d833b87ebc00)
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begin $display("E"); $finish; end
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#10;
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if (out !== 128'hdda97ca4864cdfe06eaf70a0ec0d7191)
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begin $display("E"); $finish; end
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$display("Good.");
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$finish;
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end
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always #5 clk = ~clk;
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endmodule
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