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82 lines
2.6 KiB
Verilog
82 lines
2.6 KiB
Verilog
/*
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* Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/* one AES round for every two clock cycles */
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module one_round (clk, state_in, key, state_out);
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input clk;
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input [127:0] state_in, key;
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output reg [127:0] state_out;
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wire [31:0] s0, s1, s2, s3,
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z0, z1, z2, z3,
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p00, p01, p02, p03,
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p10, p11, p12, p13,
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p20, p21, p22, p23,
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p30, p31, p32, p33,
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k0, k1, k2, k3;
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assign {k0, k1, k2, k3} = key;
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assign {s0, s1, s2, s3} = state_in;
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table_lookup
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t0 (clk, s0, p00, p01, p02, p03),
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t1 (clk, s1, p10, p11, p12, p13),
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t2 (clk, s2, p20, p21, p22, p23),
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t3 (clk, s3, p30, p31, p32, p33);
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assign z0 = p00 ^ p11 ^ p22 ^ p33 ^ k0;
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assign z1 = p03 ^ p10 ^ p21 ^ p32 ^ k1;
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assign z2 = p02 ^ p13 ^ p20 ^ p31 ^ k2;
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assign z3 = p01 ^ p12 ^ p23 ^ p30 ^ k3;
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always @ (posedge clk)
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state_out <= {z0, z1, z2, z3};
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endmodule
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/* AES final round for every two clock cycles */
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module final_round (clk, state_in, key_in, state_out);
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input clk;
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input [127:0] state_in;
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input [127:0] key_in;
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output reg [127:0] state_out;
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wire [31:0] s0, s1, s2, s3,
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z0, z1, z2, z3,
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k0, k1, k2, k3;
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wire [7:0] p00, p01, p02, p03,
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p10, p11, p12, p13,
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p20, p21, p22, p23,
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p30, p31, p32, p33;
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assign {k0, k1, k2, k3} = key_in;
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assign {s0, s1, s2, s3} = state_in;
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S4
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S4_1 (clk, s0, {p00, p01, p02, p03}),
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S4_2 (clk, s1, {p10, p11, p12, p13}),
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S4_3 (clk, s2, {p20, p21, p22, p23}),
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S4_4 (clk, s3, {p30, p31, p32, p33});
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assign z0 = {p00, p11, p22, p33} ^ k0;
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assign z1 = {p10, p21, p32, p03} ^ k1;
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assign z2 = {p20, p31, p02, p13} ^ k2;
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assign z3 = {p30, p01, p12, p23} ^ k3;
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always @ (posedge clk)
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state_out <= {z0, z1, z2, z3};
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endmodule
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