Andreas Olofsson 781121fc61 Cleanup ...

-setting DMA access to zero for now
-taking away wait for elink2 (messes up the access pattern)
-fixing typo in register mape ERX

2015-05-02 23:04:13 -04:00

..

ecfg_clocks.v

Clock/reset fixes

2015-05-02 22:42:33 -04:00

ecfg_if.v

Fixed verilog syntax issue

2015-05-02 23:03:14 -04:00

ecfg_rx.v

Complete redesign of configuration register file

2015-05-01 17:58:16 -04:00

ecfg_tx.v

Complete redesign of configuration register file

2015-05-01 17:58:16 -04:00

ecfg.v

Message box working...

2015-04-19 21:55:07 -04:00

eclocks.v

Clock/reset fixes

2015-05-02 22:42:33 -04:00

elink_constants.v

Adding constants to handle model

2015-05-02 21:30:26 -04:00

elink_regmap.v

Cleanup

2015-05-02 23:04:13 -04:00

elink.v

Fixing ecfg_clocks

2015-05-02 22:40:27 -04:00

emaxi.v

Bug fix, missing pipeline stage on read response

2015-04-21 17:14:30 -04:00

ememory.v

Memory bug fix

2015-04-26 08:29:50 -04:00

ereset.v

Cleanup

2015-05-01 17:31:45 -04:00

erx_disty.v

Updated to fit new ERX_RR register

2015-05-01 17:53:55 -04:00

erx_io.v

Address remapping integration

2015-04-24 17:39:05 -04:00

erx_protocol.v

Bypass erx remap on all ID matches

2015-04-28 16:58:05 -04:00

erx_remap.v

Bypass erx remap on all ID matches

2015-04-28 16:58:05 -04:00

erx_timer.v

Adding timeout circuit

2015-04-27 16:02:15 -04:00

erx.v

Instance renaming

2015-05-01 18:19:36 -04:00

esaxi.v

File cleanup

2015-04-23 18:10:07 -04:00

etx_arbiter.v

Cleanup

2015-05-02 23:04:13 -04:00

etx_io.v

Address remapping integration

2015-04-24 17:39:05 -04:00

etx_protocol.v

Added testmode to transmitter

2015-05-01 17:47:24 -04:00

etx_remap.v

Added bit to etx_remap

2015-04-28 16:56:31 -04:00

etx.v

Instance renaming

2015-05-01 18:19:36 -04:00