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100 lines
3.0 KiB
Verilog
100 lines
3.0 KiB
Verilog
module spi (/*AUTOARG*/
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// Outputs
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spi_irq, access_out, packet_out, wait_out, m_sclk, m_mosi, m_ss,
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s_miso,
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// Inputs
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nreset, clk, master_mode, access_in, packet_in, wait_in, m_miso,
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s_sclk, s_mosi, s_ss
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);
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//##################################################################
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//# INTERFACE
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//##################################################################
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parameter AW = 32; // data width of fifo
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parameter PW = 2*AW+40; // packet size
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parameter DEPTH = 32; // fifo depth
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//clk, reset, irq
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input nreset; // asynch active low reset
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input clk; // core clock
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input master_mode;// master mode selector
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//interrupt output
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output spi_irq; // interrupt output
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//packet from core
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input access_in; // access from core
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input [PW-1:0] packet_in; // packet from core
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input wait_in; // pushback from io
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//packet to core
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output access_out; // access to core
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output [PW-1:0] packet_out; // packet to core
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output wait_out; // pushback from core
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//master io interface
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output m_sclk; // master clock
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output m_mosi; // master output
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output m_ss; // slave select
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input m_miso; // master input
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//slave io interface
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input s_sclk; // slave clock
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input s_mosi; // slave input
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input s_ss; // slave select
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output s_miso; // slave output
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/*spi_master AUTO_TEMPLATE (.clk (clk),
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.nreset (nreset),
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.\(.*\)_in (\1_in[]),
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.\(.*\) (m_\1[]),
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);
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*/
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spi_master spi_master (/*AUTOINST*/
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// Outputs
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.sclk (m_sclk), // Templated
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.mosi (m_mosi), // Templated
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.ss (m_ss), // Templated
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.wait_out (m_wait_out), // Templated
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.access_out (m_access_out), // Templated
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.packet_out (m_packet_out[PW-1:0]), // Templated
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// Inputs
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.clk (clk), // Templated
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.nreset (nreset), // Templated
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.miso (m_miso), // Templated
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.access_in (access_in), // Templated
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.packet_in (packet_in[PW-1:0]), // Templated
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.wait_in (wait_in)); // Templated
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/*spi_slave AUTO_TEMPLATE (.clk (clk),
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.nreset (nreset),
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.\(.*\)_in (\1_in[]),
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.\(.*\) (m_\1[]),
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);
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*/
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spi_slave spi_slave (/*AUTOINST*/
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// Outputs
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.spi_regs (m_spi_regs[SREGS*8-1:0]), // Templated
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.miso (m_miso), // Templated
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.core_spi_access(m_core_spi_access), // Templated
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.core_spi_packet(m_core_spi_packet[PW-1:0]), // Templated
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.core_spi_wait (m_core_spi_wait), // Templated
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// Inputs
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.clk (clk), // Templated
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.nreset (nreset), // Templated
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.sclk (m_sclk), // Templated
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.mosi (m_mosi), // Templated
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.ss (m_ss), // Templated
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.core_access (m_core_access), // Templated
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.core_packet (m_core_packet[PW-1:0])); // Templated
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endmodule // spi
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