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OH!

An Open Hardware Model Library for Chip and FPGA Designers

The library is written in vanilla Verilog. Pull requests accepted.

Spec	Status	Description
eaxi		AXI network interface stuff
common		Common modules (synchronizer etc)
edma		Basic DMA module
emesh		Epiphany emesh related circuits
elink		Epiphany point to point LVDS link
emailbox		Simple mailbox with interrupt output
emmu		Simple memory transaction translation unit
memory		Various simple memory structures (RAM/FIFO)
rand		Random number generators
xilibs		Simulation modules for Xilinx primitives

LICENSE

This library is made available with a GPL V3 copyleft license with the added condition that the Verilog code herein is to be considered software and physical chips and FPGA bitstreams are the hardware equivalent of a binary program.