Andreas Olofsson bc53400888 Adding parallella block design ...

-Start with gui
-Generate block design
-Edit text, this is f'ing crazy!
-If this is the only way to use the vivado IP not sure I want it
-Strive towards doing everything in verilog
-Split into:
1.) Verilog block (no IP!)
2.) One top level to instantiate IP + clean verilog block
-Never fight the tools..

2015-05-22 21:38:39 -04:00

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xilinx

Adding parallella block design

2015-05-22 21:38:39 -04:00