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40 lines
818 B
Verilog
40 lines
818 B
Verilog
module oh_clockgate(/*AUTOARG*/
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// Outputs
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eclk,
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// Inputs
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nrst, clk, en, se
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);
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parameter DW=1;
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input nrst;//active low reset
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input clk; //clock input
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input se; //scan enable
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input [DW-1:0] en; //enable (from positive edge FF)
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output [DW-1:0] eclk;//enabled clock
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`ifdef CFG_ASIC
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`else
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wire [DW-1:0] en_sh;
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wire [DW-1:0] en_sl;
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//Turn on clock if in scan mode or if enabled
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assign en_sl[DW-1:0] = en[DW-1:0] |
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{(DW){se}} |
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{(DW){~nrst}};
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//making signal stable
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oh_lat0 #(.DW(1)) lat0 (.out_sh (en_sh[DW-1:0]),
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.in_sl (en_sl[DW-1:0]),
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.clk (clk)
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);
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assign eclk[DW-1:0] = {(DW){clk}} & en_sh[DW-1:0];
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`endif
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endmodule // clock_gater
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