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56 lines
1.2 KiB
Verilog
56 lines
1.2 KiB
Verilog
// # rising edge FF (output in_sl) follwowed by falling edge FF
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// # has the following schematic representation:
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// #
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// # posedge FF -> negedge FF
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// # || ||
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// # \/ \/
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// # lat0-lat1 -> lat1-lat0
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// # ||
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// # \/
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// # lat0-lat1 -> lat0
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// # || ||
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// # \/ \/
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// # posedge FF -> lat0
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module oh_lat0 (/*AUTOARG*/
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// Outputs
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out_sh,
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// Inputs
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in_sl, clk
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);
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parameter DW=99;
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input [DW-1:0] in_sl;
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input clk;
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output [DW-1:0] out_sh;
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reg [DW-1:0] out_real_sh;
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/* verilator lint_off COMBDLY */
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// # Real lat0
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always @ (clk or in_sl)
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if (~clk)
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out_real_sh[DW-1:0] <= in_sl[DW-1:0];
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/* verilator lint_on COMBDLY */
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`ifdef DV_FAKELAT
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// # negedge FF
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reg [DW-1:0] out_dv_sh;
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always @ (negedge clk)
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out_dv_sh[DW-1:0] <= in_sl[DW-1:0];
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assign out_sh[DW-1:0] = out_dv_sh[DW-1:0];
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// #########################################
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`else // !`ifdef DV_FAKELAT
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// #########################################
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assign out_sh[DW-1:0] = out_real_sh[DW-1:0];
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// #########################################
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`endif // !`ifdef CFG_FAKELAT
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endmodule // oh_lat0
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