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oh/parallella/fpga
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Andreas Olofsson a5194a30a3 Reorg 
-Renaming constants files as ".vh"
-Cleanup parameters
2016-02-26 19:08:40 -05:00
..
headless
Reorg
2016-02-26 19:08:40 -05:00
parallella_accelerator
Adding IP packaging files
2016-01-20 17:36:57 -05:00
parallella_base
Moving axi cells to own folder
2015-12-04 03:38:26 -05:00
sdr_fmcomms
Adding skeleton for adi sdr design
2015-11-11 00:42:14 -05:00
Makefile
Added Makefiles to make build easier
2015-11-29 14:44:21 +00:00
parallella_7020_io.xdc
Fixing typos
2015-11-06 22:40:59 -05:00
parallella_io.xdc
Reorg
2016-02-26 19:08:40 -05:00
parallella_timing.xdc
Fixing system_bd interface for "mailbox_irq" signal
2015-11-29 12:41:53 -05:00
README.md
Updated system memory map
2015-11-06 20:44:18 -05:00

README.md

P1600: 7010 + 0 GPIO P1601: 7010 + 24 GPIO P1602: 7020 + 48 GPIO A101010: 7010 + 0 GPIO A101020: 7010 + 24 GPIO A101040: 7020 + 48 GPIO

parallella_headless.tcl --product number as argument parallella_display.tcl parallella_sdr.tcl

EDITING SYSTEM>BD IN GUI (ONE TIME..)

  1. create ports
  2. connect wires
  3. run connection automation
  4. create memory map
  5. validate_bd_design
  6. write_bd_tcl ./system_bd.tcl

DESIGN LOOP

  1. Make verilog change..
  2. cd parallella_base; ./build.sh
  3. cd ../headless;; ./build.sh
  4. profit