mirror of
https://github.com/aolofsson/oh.git
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116 lines
3.7 KiB
Verilog
116 lines
3.7 KiB
Verilog
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// Implements GPIO pins from the PS/EMIO
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// Works with 7010 (24 pins) or 7020 (48 pins) and
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// either single-ended or differential IO
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module pgpio(/*AUTOARG*/
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// Outputs
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ps_gpio_i,
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// Inouts
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gpio_p, gpio_n,
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// Inputs
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ps_gpio_o, ps_gpio_t
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);
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parameter NGPIO = 24; // 12 or 24
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parameter NPS = 64; // signals for PS
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parameter DIFF = 0; // 0= single ended
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// 1= differential
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inout [NGPIO-1:0] gpio_p;
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inout [NGPIO-1:0] gpio_n;
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output [NPS-1:0] ps_gpio_i;
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input [NPS-1:0] ps_gpio_o;
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input [NPS-1:0] ps_gpio_t;
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genvar m;
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generate
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if( DIFF == 1 ) begin: gpio_diff
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IOBUFDS
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#(
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.DIFF_TERM("TRUE"),
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.IBUF_LOW_PWR("TRUE"),
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.IOSTANDARD("LVDS_25"),
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.SLEW("FAST")
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)
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i_iodiff [NGPIO-1:0]
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(
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.O(ps_gpio_i), // Buffer output
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.IO(gpio_p), // Diff_p inout (connect directly to top-level port)
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.IOB(gpio_n), // Diff_n inout (connect directly to top-level port)
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.I(ps_gpio_o), // Buffer input
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.T(ps_gpio_t) // 3-state enable input, high=input, low=output
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);
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end else begin: gpio_cmos // single-ended
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wire [NGPIO-1:0] gpio_i_n, gpio_i_p;
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wire [NGPIO-1:0] gpio_o_n, gpio_o_p;
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wire [NGPIO-1:0] gpio_t_n, gpio_t_p;
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// Map P/N pins to single-ended signals
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for(m=0; m<NGPIO; m=m+2) begin : assign_se_sigs
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assign ps_gpio_i[2*m] = gpio_i_n[m];
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assign ps_gpio_i[2*m+1] = gpio_i_n[m+1];
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assign ps_gpio_i[2*m+2] = gpio_i_p[m];
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assign ps_gpio_i[2*m+3] = gpio_i_p[m+1];
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assign gpio_o_n[m] = ps_gpio_o[2*m];
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assign gpio_o_n[m+1] = ps_gpio_o[2*m+1];
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assign gpio_o_p[m] = ps_gpio_o[2*m+2];
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assign gpio_o_p[m+1] = ps_gpio_o[2*m+3];
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assign gpio_t_n[m] = ps_gpio_t[2*m];
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assign gpio_t_n[m+1] = ps_gpio_t[2*m+1];
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assign gpio_t_p[m] = ps_gpio_t[2*m+2];
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assign gpio_t_p[m+1] = ps_gpio_t[2*m+3];
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end // block: assign_se_sigs
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IOBUF
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#(
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.DRIVE(8), // Specify the output drive strength
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.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
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.IOSTANDARD("LVCMOS25"), // Specify the I/O standard
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.SLEW("SLOW") // Specify the output slew rate
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)
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i_iocmos_n [NGPIO-1:0]
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(
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.O(gpio_i_n), // Buffer output
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.IO(gpio_n), // Buffer inout port (connect directly to top-level port)
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.I(gpio_o_n), // Buffer input
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.T(gpio_t_n) // 3-state enable input, high=input, low=output
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);
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IOBUF
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#(
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.DRIVE(8), // Specify the output drive strength
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.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
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.IOSTANDARD("LVCMOS25"), // Specify the I/O standard
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.SLEW("SLOW") // Specify the output slew rate
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)
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i_iocmos_p [NGPIO-1:0]
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(
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.O(gpio_i_p), // Buffer output
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.IO(gpio_p), // Buffer inout port (connect directly to top-level port)
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.I(gpio_o_p), // Buffer input
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.T(gpio_t_p) // 3-state enable input, high=input, low=output
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);
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end // block: GPIO_SE
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endgenerate
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// Tie off unused PS EMIO signals for now
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genvar i;
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generate
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for (i=NGPIO*2;i<NPS;i=i+1)
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assign ps_gpio_i[i] = 1'b0;
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endgenerate
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endmodule // parallella_gpio_emio
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