Andreas Olofsson e549a63a04 Reorg/cleanup

2016-03-08 19:37:42 -05:00

..

BUF.v

dummy

2015-10-07 11:58:35 -04:00

BUFG.v

Cleanup

2015-04-21 21:43:16 -04:00

BUFIO.v

Adding comments

2015-04-23 17:52:46 -04:00

BUFR.v

Cleanup

2015-05-07 23:49:50 -04:00

CLKDIV.v

Adding clkdivider model

2016-02-26 19:03:25 -05:00

fifo_async_104x32.v

Reorg/cleanup

2016-03-08 19:37:42 -05:00

fifo_generator_vlog_beh.v

Reorg/cleanup

2016-03-08 19:37:42 -05:00

IBUF_IBUFDISABLE.v

Adding dummy cells

2015-10-07 11:57:52 -04:00

IBUF_INTERMDISABLE.v

Adding dummy cells

2015-10-07 11:57:52 -04:00

IBUF.v

Adding dummy cells

2015-10-07 11:57:52 -04:00

IBUFDS_DIFF_OUT.v

Adding dummy cells

2015-10-07 11:57:52 -04:00

IBUFDS_GTE2.v

Adding dummy cells

2015-10-07 11:57:52 -04:00

IBUFDS_IBUFDISABLE_INT.v

Adding dummy cells

2015-10-07 11:57:52 -04:00

IBUFDS_IBUFDISABLE.v

Adding dummy cells

2015-10-07 11:57:52 -04:00

IBUFDS_INTERMDISABLE_INT.v

Adding dummy cells

2015-10-07 11:57:52 -04:00

IBUFDS_INTERMDISABLE.v

Adding dummy cells

2015-10-07 11:57:52 -04:00

IBUFDS.v

Adding comments

2015-04-23 17:52:46 -04:00

IBUFE3.v

Adding dummy cells

2015-10-07 11:57:52 -04:00

IBUFGDS.v

Adding comments

2015-04-23 17:52:46 -04:00

IDDR.v

Hold hack..

2016-01-19 16:01:15 -05:00

IDELAYCTRL.v

Adding hack model for RDY signal

2015-10-07 19:18:54 -04:00

IDELAYE2_FINEDELAY.v

Adding dummy cells

2015-10-07 11:57:52 -04:00

IDELAYE2.v

Timescale stuff

2015-11-13 16:25:38 -05:00

IDELAYE3.v

Adding dummy cells

2015-10-07 11:57:52 -04:00

IOBUF_INTERMDISABLE.v

Adding dummy cells

2015-10-07 11:57:52 -04:00

IOBUF.v

Bulk edits (clean up later)

2015-11-06 07:03:28 -05:00

IOBUFDS_DCIEN.v

Adding dummy cells

2015-10-07 11:57:52 -04:00

IOBUFDS_DIFF_OUT_INTERMDISABLE.v

Adding dummy cells

2015-10-07 11:57:52 -04:00

IOBUFDS.v

Fixing empty models

2015-11-06 07:02:28 -05:00

IOBUFDSE3.v

Adding dummy cells

2015-10-07 11:57:52 -04:00

ISERDESE2.v

Adding warning message to ISERDES/OSERDES

2015-05-13 23:33:26 -04:00

MMCME2_ADV.v

Creating new "CLKDIV" module

2016-02-26 16:56:56 -05:00

OBUF.v

Adding OBUF model

2015-06-25 15:42:20 -04:00

OBUFDS_GTE3_ADV.v

Adding dummy cells

2015-10-07 11:57:52 -04:00

OBUFDS.v

Comments

2015-04-23 17:52:06 -04:00

OBUFT.v

Fixing empty models

2015-11-06 07:02:28 -05:00

OBUFTDS_DCIEN.v

Adding dummy cells

2015-10-07 11:57:52 -04:00

OBUFTDS.v

Cleanup

2015-04-21 21:43:16 -04:00

ODDR.v

Fixing reset behavioral bug

2015-10-07 19:17:35 -04:00

ODELAYE2.v

Adding PLL and MMCME2 primitives

2015-04-22 13:55:59 -04:00

OSERDESE2.v

Adding warning message to ISERDES/OSERDES

2015-05-13 23:33:26 -04:00

PLLE2_ADV.v

Creating new "CLKDIV" module

2016-02-26 16:56:56 -05:00

PLLE2_BASE.v

Fixing bug in clock frequency parameter

2015-05-07 23:49:07 -04:00

RAM32X1D.v

Cleanup

2015-04-21 21:43:16 -04:00