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27 lines
481 B
Verilog
27 lines
481 B
Verilog
/*An empty IDELAYCTRL model*/
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module IDELAYCTRL (/*AUTOARG*/
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// Outputs
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RDY,
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// Inputs
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REFCLK, RST
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);
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output RDY; //goes high when delay has been calibrated
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input REFCLK; //reference clock for setting tap delay
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input RST; //reset pulse for setting
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reg RDY;
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always @ (posedge REFCLK or posedge RST)
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if(RST)
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RDY <= 1'b0;
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else
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RDY <= 1'b1; //one clock cycle on REFCLK
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endmodule // IDELAYCTRL
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