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c627827a6b
-Adding model (one source..) -generate for 104x32 for xilinx -making prog_full the default full indicator -bringing out almost_full for future use -fixing interface change in all modules
37 lines
1.6 KiB
Verilog
37 lines
1.6 KiB
Verilog
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
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// --------------------------------------------------------------------------------
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// Tool Version: Vivado v.2014.3.1 (lin64) Build 1056140 Thu Oct 30 16:30:39 MDT 2014
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// Date : Thu Jul 2 14:31:27 2015
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// Host : parallella running 64-bit Ubuntu 14.04.2 LTS
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// Command : write_verilog -force -mode synth_stub
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// /home/aolofsson/Work_all/oh/elink/scripts/xilinx/temp/temp.srcs/sources_1/ip/fifo_async_104x16/fifo_async_104x16_stub.v
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// Design : fifo_async_104x16
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// Purpose : Stub declaration of top-level module interface
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// Device : xc7z020clg484-1
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// --------------------------------------------------------------------------------
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// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
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// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
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// Please paste the declaration into a Verilog source file or add the file as an additional source.
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(* x_core_info = "fifo_generator_v12_0,Vivado 2014.3.1" *)
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module fifo_async_104x16(wr_clk, wr_rst, rd_clk, rd_rst, din, wr_en, rd_en, dout, full, almost_full, empty, valid, prog_full)
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/* synthesis syn_black_box black_box_pad_pin="wr_clk,wr_rst,rd_clk,rd_rst,din[103:0],wr_en,rd_en,dout[103:0],full,almost_full,empty,valid,prog_full" */;
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input wr_clk;
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input wr_rst;
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input rd_clk;
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input rd_rst;
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input [103:0]din;
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input wr_en;
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input rd_en;
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output [103:0]dout;
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output full;
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output almost_full;
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output empty;
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output valid;
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output prog_full;
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endmodule
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