FPGA/oh

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Andreas Olofsson 31e721cea7 Interface change

Changed to packet interface
Changed name to "mailbox"

2015-04-23 17:54:59 -04:00

common

Adding emesh to packet converters

2015-04-22 16:43:52 -04:00

edma

Adding an emesh DMA

2015-04-23 17:49:06 -04:00

elink

Splitting register file (rx,tx,base)

2015-04-23 17:50:45 -04:00

emailbox/hdl

Interface change

2015-04-23 17:54:59 -04:00

embox

Adding basic readme files

2015-04-21 21:49:40 -04:00

emmu

Changing to packet interface

2015-04-23 17:54:23 -04:00

memory

Changing FIFO interface

2015-04-23 17:53:22 -04:00

xilibs

Adding comments

2015-04-23 17:52:46 -04:00

.gitignore

Cleanup

2015-04-21 21:43:16 -04:00

CONTRIBUTING.md

Basic infrastructure

2015-04-21 21:36:37 -04:00

COPYING

Basic infrastructure

2015-04-21 21:36:37 -04:00

LICENSE

Initial commit

2015-04-21 21:16:42 -04:00

README.md

Massive commit sequence coming...

2015-04-23 17:48:12 -04:00

README.md

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OH!

Open Hardware (Pure and Simple)

(work in progress...)

Languages

Verilog 81.1%

Tcl 10.7%

C 5.6%

Shell 0.8%

Python 0.6%

Other 1.2%