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40 lines
809 B
Verilog
40 lines
809 B
Verilog
//A reset signal synchronizer
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//Async entry, synchronous exit!
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module rsync (/*AUTOARG*/
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// Outputs
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nrst_out,
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// Inputs
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clk, nrst_in
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);
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parameter PS = 2; //number of sync pipeline stages
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parameter DW = 1; //number of bits to synchronize
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input clk;
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input [DW-1:0] nrst_in;
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output [DW-1:0] nrst_out;
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reg [PS-1:0] sync_pipe[DW-1:0];
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genvar i;
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integer j;
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generate
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for(i=0;i<DW;i=i+1)
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begin
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always @ (posedge clk or negedge nrst_in[i])
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if(!nrst_in[i])
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sync_pipe[i] <= 'b0;
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else
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begin
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sync_pipe[i][0] =1'b1;
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for(j=1;j<PS;j=j+1)
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sync_pipe[i][j] = sync_pipe[i][j-1];
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end
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assign nrst_out[i] = sync_pipe[i][PS-1];
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end
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endgenerate
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endmodule // rsync
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