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983c4db449
- Using new packet interface - Adding active signal, indicating that link is ready. This way you don't need to guess when the link is ready (no magic constants) - Removed register on por reset input to get rid of x on startup.
12 lines
298 B
Verilog
12 lines
298 B
Verilog
`ifndef ELINK_CONSTANTS_V_
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`define ELINK_CONSTANTS_V_
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//These constants are mutually exclusive
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`define TARGET_XILINX //uncomment for non-xilinx platforms
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`define CFG_AW 32
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`define CFG_DW 32
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`define CFG_LW 8
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`define CFG_NW 13 /*Number of bytes in the transmission*/
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`endif
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