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191 lines
7.7 KiB
Verilog
191 lines
7.7 KiB
Verilog
//#############################################################################
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//# Purpose: A DMA ENGINE #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see below) #
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//#############################################################################
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module edma #( parameter AW = 32, // address width
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parameter PW = 104 // packet width
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)
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(
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// power
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input vdd, // supply
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input vss, // common ground
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// reset, clk, config
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input clk, // main core clock
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input nreset, // async active low reset
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output irq, // interrupt output
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// datapath interface
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input access_in, // streaming input access
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input [PW-1:0] packet_in, // streaming input data
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output wait_out, // pushback
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output access_out, // output access (master/slave)
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output [PW-1:0] packet_out, // output packet (with address)
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input wait_in, // pushback
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// config/fetch interface
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input reg_access_in, // config register access
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input [PW-1:0] reg_packet_in, // config register packet
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output reg_wait_out, // pushback by register read
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output reg_access_out,// config readback
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output [PW-1:0] reg_packet_out,// config reacback packet
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input reg_wait_in // pushback for readback
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);
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//###############
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//# LOCAL WIRES
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//###############
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/*AUTOOUTPUT*/
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire chainmode; // From edma_regs of edma_regs.v
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wire [31:0] count; // From edma_dp of edma_dp.v
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wire [31:0] count_reg; // From edma_regs of edma_regs.v
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wire [4:0] ctrlmode; // From edma_regs of edma_regs.v
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wire [15:0] curr_descr; // From edma_regs of edma_regs.v
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wire [1:0] datamode; // From edma_regs of edma_regs.v
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wire dma_en; // From edma_regs of edma_regs.v
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wire [3:0] dma_state; // From edma_ctrl of edma_ctrl.v
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wire [AW-1:0] dstaddr; // From edma_dp of edma_dp.v
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wire [63:0] dstaddr_reg; // From edma_regs of edma_regs.v
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wire fetch_access; // From edma_ctrl of edma_ctrl.v
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wire [PW-1:0] fetch_packet; // From edma_ctrl of edma_ctrl.v
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wire manualmode; // From edma_regs of edma_regs.v
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wire master_active; // From edma_ctrl of edma_ctrl.v
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wire mastermode; // From edma_regs of edma_regs.v
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wire [15:0] next_descr; // From edma_regs of edma_regs.v
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wire [AW-1:0] srcaddr; // From edma_dp of edma_dp.v
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wire [63:0] srcaddr_reg; // From edma_regs of edma_regs.v
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wire [31:0] stride_reg; // From edma_regs of edma_regs.v
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wire update; // From edma_ctrl of edma_ctrl.v
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wire update2d; // From edma_ctrl of edma_ctrl.v
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// End of automatics
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//##########################
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//# DATAPATH
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//##########################
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edma_dp #(.AW(AW),
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.PW(PW))
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edma_dp(/*AUTOINST*/
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// Outputs
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.count (count[31:0]),
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.srcaddr (srcaddr[AW-1:0]),
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.dstaddr (dstaddr[AW-1:0]),
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.wait_out (wait_out),
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.access_out (access_out),
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.packet_out (packet_out[PW-1:0]),
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// Inputs
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.clk (clk),
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.nreset (nreset),
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.master_active (master_active),
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.update2d (update2d),
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.datamode (datamode[1:0]),
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.ctrlmode (ctrlmode[4:0]),
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.stride_reg (stride_reg[31:0]),
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.count_reg (count_reg[31:0]),
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.srcaddr_reg (srcaddr_reg[AW-1:0]),
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.dstaddr_reg (dstaddr_reg[AW-1:0]),
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.access_in (access_in),
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.packet_in (packet_in[PW-1:0]),
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.wait_in (wait_in));
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//##########################
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//# CONFIG REGISTERS
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//##########################
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edma_regs #(.AW(AW),
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.PW(PW))
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edma_regs (/*AUTOINST*/
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// Outputs
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.reg_wait_out (reg_wait_out),
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.reg_access_out (reg_access_out),
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.reg_packet_out (reg_packet_out[PW-1:0]),
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.dma_en (dma_en),
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.mastermode (mastermode),
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.manualmode (manualmode),
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.datamode (datamode[1:0]),
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.ctrlmode (ctrlmode[4:0]),
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.chainmode (chainmode),
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.irq (irq),
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.next_descr (next_descr[15:0]),
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.curr_descr (curr_descr[15:0]),
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.stride_reg (stride_reg[31:0]),
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.count_reg (count_reg[31:0]),
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.dstaddr_reg (dstaddr_reg[63:0]),
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.srcaddr_reg (srcaddr_reg[63:0]),
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// Inputs
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.clk (clk),
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.nreset (nreset),
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.reg_access_in (reg_access_in),
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.reg_packet_in (reg_packet_in[PW-1:0]),
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.reg_wait_in (reg_wait_in),
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.fetch_access (fetch_access),
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.fetch_packet (fetch_packet[PW-1:0]),
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.count (count[31:0]),
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.dstaddr (dstaddr[AW-1:0]),
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.srcaddr (srcaddr[AW-1:0]),
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.dma_state (dma_state[3:0]),
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.update (update));
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//##########################
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//# STATE MACHINE
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//##########################
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edma_ctrl #(.AW(AW),
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.PW(PW))
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edma_ctrl (/*AUTOINST*/
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// Outputs
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.fetch_access (fetch_access),
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.fetch_packet (fetch_packet[PW-1:0]),
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.dma_state (dma_state[3:0]),
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.update (update),
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.update2d (update2d),
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.master_active (master_active),
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// Inputs
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.clk (clk),
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.nreset (nreset),
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.dma_en (dma_en),
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.chainmode (chainmode),
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.manualmode (manualmode),
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.mastermode (mastermode),
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.count (count[31:0]),
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.curr_descr (curr_descr[15:0]),
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.next_descr (next_descr[15:0]),
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.reg_wait_in (reg_wait_in),
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.access_in (access_in),
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.wait_in (wait_in));
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endmodule // edma
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// Local Variables:
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// verilog-library-directories:("." "../hdl" "../../common/hdl")
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// End:
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///////////////////////////////////////////////////////////////////////////////
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// The MIT License (MIT) //
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// //
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// Copyright (c) 2015-2016, Adapteva, Inc. //
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// //
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// Permission is hereby granted, free of charge, to any person obtaining a //
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// copy of this software and associated documentation files (the "Software") //
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// to deal in the Software without restriction, including without limitation //
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// the rights to use, copy, modify, merge, publish, distribute, sublicense, //
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// and/or sell copies of the Software, and to permit persons to whom the //
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// Software is furnished to do so, subject to the following conditions: //
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// //
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// The above copyright notice and this permission notice shall be included //
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// in all copies or substantial portions of the Software. //
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// //
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS //
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// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF //
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// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. //
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// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY //
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// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT //
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// OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR //
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// THE USE OR OTHER DEALINGS IN THE SOFTWARE. //
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// //
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///////////////////////////////////////////////////////////////////////////////
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