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494 lines
19 KiB
Verilog
494 lines
19 KiB
Verilog
module etx(/*AUTOARG*/
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// Outputs
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chipid, txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n,
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txo_data_p, txo_data_n, txrd_wait, txwr_wait, txrr_wait,
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etx_cfg_access, etx_cfg_packet,
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// Inputs
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reset, sys_clk, tx_lclk, tx_lclk90, tx_lclk_div4, testmode,
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txi_wr_wait_p, txi_wr_wait_n, txi_rd_wait_p, txi_rd_wait_n,
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txrd_access, txrd_packet, txwr_access, txwr_packet, txrr_access,
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txrr_packet, etx_cfg_wait
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);
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parameter AW = 32;
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parameter DW = 32;
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parameter PW = 104;
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parameter RFAW = 6;
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parameter ID = 12'h000;
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//Clocks,reset,config
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input reset;
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input sys_clk;
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input tx_lclk; // high speed serdes clock
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input tx_lclk90; // lclk for output
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input tx_lclk_div4; // slow speed parallel clock
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input testmode; // hardware pin, generates continuous transmit pattern
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output [11:0] chipid; //id for epiphany chip
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//Transmit signals for IO
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output txo_lclk_p, txo_lclk_n; //tx center aligned clock (>500MHz)
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output txo_frame_p, txo_frame_n; //tx frame signal
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output [7:0] txo_data_p, txo_data_n; //tx data (dual data rate)
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input txi_wr_wait_p,txi_wr_wait_n; //tx async write pushback
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input txi_rd_wait_p, txi_rd_wait_n; //tx async read pushback
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//Read Request Channel Input
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input txrd_access;
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input [PW-1:0] txrd_packet;
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output txrd_wait;
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//Write Channel Input
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input txwr_access;
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input [PW-1:0] txwr_packet;
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output txwr_wait;
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//Read Response Channel Input
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input txrr_access;
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input [PW-1:0] txrr_packet;
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output txrr_wait;
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//Configuration Interface (for ERX)
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output etx_cfg_access;
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output [PW-1:0] etx_cfg_packet;
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input etx_cfg_wait;
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//debug declarations
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wire[15:0] tx_status;
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wire txwr_fifo_full;//todo-fix
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wire txrr_fifo_full;
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wire txrd_fifo_full;
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/*AUTOOUTPUT*/
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [3:0] ctrlmode; // From ecfg_tx of ecfg_tx.v
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wire ctrlmode_bypass; // From ecfg_tx of ecfg_tx.v
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wire edma_access; // From edma of edma.v
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wire [PW-1:0] edma_packet; // From edma of edma.v
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wire edma_wait; // From etx_arbiter of etx_arbiter.v
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wire emmu_access; // From emmu of emmu.v
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wire [PW-1:0] emmu_packet; // From emmu of emmu.v
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wire etx_access; // From etx_arbiter of etx_arbiter.v
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wire etx_io_wait; // From etx_protocol of etx_protocol.v
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wire [PW-1:0] etx_packet; // From etx_arbiter of etx_arbiter.v
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wire etx_rd_wait; // From etx_protocol of etx_protocol.v
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wire etx_remap_access; // From etx_remap of etx_remap.v
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wire [PW-1:0] etx_remap_packet; // From etx_remap of etx_remap.v
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wire etx_rr; // From etx_arbiter of etx_arbiter.v
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wire etx_wait; // From etx_protocol of etx_protocol.v
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wire etx_wr_wait; // From etx_protocol of etx_protocol.v
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wire [8:0] gpio_data; // From ecfg_tx of ecfg_tx.v
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wire gpio_enable; // From ecfg_tx of ecfg_tx.v
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wire [14:0] mi_addr; // From ecfg_if of ecfg_if.v
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wire [DW-1:0] mi_cfg_dout; // From ecfg_tx of ecfg_tx.v
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wire mi_cfg_en; // From ecfg_if of ecfg_if.v
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wire [63:0] mi_din; // From ecfg_if of ecfg_if.v
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wire [DW-1:0] mi_dma_dout; // From edma of edma.v
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wire mi_dma_en; // From ecfg_if of ecfg_if.v
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wire [DW-1:0] mi_mmu_dout; // From emmu of emmu.v
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wire mi_mmu_en; // From ecfg_if of ecfg_if.v
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wire mi_we; // From ecfg_if of ecfg_if.v
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wire mmu_enable; // From ecfg_tx of ecfg_tx.v
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wire remap_enable; // From ecfg_tx of ecfg_tx.v
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wire tp_enable; // From ecfg_tx of ecfg_tx.v
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wire [63:0] tx_data_par; // From etx_protocol of etx_protocol.v
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wire tx_enable; // From ecfg_tx of ecfg_tx.v
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wire [7:0] tx_frame_par; // From etx_protocol of etx_protocol.v
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wire tx_rd_wait; // From etx_io of etx_io.v
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wire tx_wr_wait; // From etx_io of etx_io.v
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wire txrd_fifo_empty; // From txrd_fifo of fifo_async.v
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wire [PW-1:0] txrd_fifo_packet; // From txrd_fifo of fifo_async.v
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wire txrd_fifo_read; // From etx_arbiter of etx_arbiter.v
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wire txrr_fifo_empty; // From txrr_fifo of fifo_async.v
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wire [PW-1:0] txrr_fifo_packet; // From txrr_fifo of fifo_async.v
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wire txrr_fifo_read; // From etx_arbiter of etx_arbiter.v
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wire txwr_fifo_empty; // From txwr_fifo of fifo_async.v
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wire [PW-1:0] txwr_fifo_packet; // From txwr_fifo of fifo_async.v
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wire txwr_fifo_read; // From etx_arbiter of etx_arbiter.v
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// End of automatics
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wire [15:0] ecfg_status; // To ecfg_tx of ecfg_tx.v
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/************************************************************/
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/*FIFOs */
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/************************************************************/
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//TODO: Minimize depth and width
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/*fifo_async AUTO_TEMPLATE (
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// Outputs
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.valid (),//TODO: Use??
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.dout (@"(substring vl-cell-name 0 4)"_fifo_packet[PW-1:0]),
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.empty (@"(substring vl-cell-name 0 4)"_fifo_empty),
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.full (@"(substring vl-cell-name 0 4)"_wait),
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.prog_full (),
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// Inputs
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.rd_clk (tx_lclk_div4),
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.wr_clk (sys_clk),
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.wr_en (@"(substring vl-cell-name 0 4)"_access),
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.rd_en (@"(substring vl-cell-name 0 4)"_fifo_read),
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.reset (reset),
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.din (@"(substring vl-cell-name 0 4)"_packet[PW-1:0]),
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);
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*/
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//Write fifo (from slave)
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fifo_async #(.DW(104), .AW(5)) txwr_fifo(
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/*AUTOINST*/
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// Outputs
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.full (txwr_wait), // Templated
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.prog_full (), // Templated
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.dout (txwr_fifo_packet[PW-1:0]), // Templated
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.empty (txwr_fifo_empty), // Templated
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.valid (), // Templated
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// Inputs
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.reset (reset), // Templated
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.wr_clk (sys_clk), // Templated
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.rd_clk (tx_lclk_div4), // Templated
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.wr_en (txwr_access), // Templated
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.din (txwr_packet[PW-1:0]), // Templated
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.rd_en (txwr_fifo_read)); // Templated
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//Read request fifo (from slave)
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fifo_async #(.DW(104), .AW(5)) txrd_fifo(
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/*AUTOINST*/
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// Outputs
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.full (txrd_wait), // Templated
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.prog_full (), // Templated
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.dout (txrd_fifo_packet[PW-1:0]), // Templated
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.empty (txrd_fifo_empty), // Templated
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.valid (), // Templated
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// Inputs
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.reset (reset), // Templated
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.wr_clk (sys_clk), // Templated
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.rd_clk (tx_lclk_div4), // Templated
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.wr_en (txrd_access), // Templated
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.din (txrd_packet[PW-1:0]), // Templated
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.rd_en (txrd_fifo_read)); // Templated
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//Read response fifo (from master)
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fifo_async #(.DW(104), .AW(5)) txrr_fifo(
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/*AUTOINST*/
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// Outputs
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.full (txrr_wait), // Templated
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.prog_full (), // Templated
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.dout (txrr_fifo_packet[PW-1:0]), // Templated
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.empty (txrr_fifo_empty), // Templated
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.valid (), // Templated
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// Inputs
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.reset (reset), // Templated
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.wr_clk (sys_clk), // Templated
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.rd_clk (tx_lclk_div4), // Templated
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.wr_en (txrr_access), // Templated
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.din (txrr_packet[PW-1:0]), // Templated
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.rd_en (txrr_fifo_read)); // Templated
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/************************************************************/
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/*EDMA ("4th channel") */
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/************************************************************/
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/*edma AUTO_TEMPLATE (.clk (tx_lclk_div4),
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.mi_en (mi_dma_en),
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.edma_access (edma_access),
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.mi_dout (mi_dma_dout[DW-1:0]),
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.edma_access (edma_access),
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.edma_write (edma_packet[1]),
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.edma_datamode (edma_packet[3:2]),
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.edma_ctrlmode (edma_packet[7:4]),
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.edma_dstaddr (edma_packet[39:8]),
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.edma_data (edma_packet[71:40]),
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.edma_srcaddr (edma_packet[103:72]),
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);
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*/
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edma etx_dma (/*AUTOINST*/
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// Outputs
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.mi_dout (mi_dma_dout[DW-1:0]), // Templated
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.edma_access (edma_access), // Templated
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.edma_packet (edma_packet[PW-1:0]),
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// Inputs
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.reset (reset),
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.clk (tx_lclk_div4), // Templated
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.mi_en (mi_dma_en), // Templated
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.mi_we (mi_we),
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.mi_addr (mi_addr[RFAW+1:0]),
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.mi_din (mi_din[63:0]),
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.edma_wait (edma_wait));
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/************************************************************/
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/*ELINK TRANSMIT ARBITER */
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/************************************************************/
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defparam etx_arbiter.ID=ID;
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etx_arbiter etx_arbiter (.clk (tx_lclk_div4),
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/*AUTOINST*/
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// Outputs
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.txwr_fifo_read (txwr_fifo_read),
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.txrd_fifo_read (txrd_fifo_read),
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.txrr_fifo_read (txrr_fifo_read),
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.edma_wait (edma_wait),
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.etx_access (etx_access),
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.etx_packet (etx_packet[PW-1:0]),
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.etx_rr (etx_rr),
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// Inputs
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.reset (reset),
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.txwr_fifo_empty (txwr_fifo_empty),
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.txwr_fifo_packet (txwr_fifo_packet[PW-1:0]),
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.txrd_fifo_empty (txrd_fifo_empty),
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.txrd_fifo_packet (txrd_fifo_packet[PW-1:0]),
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.txrr_fifo_empty (txrr_fifo_empty),
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.txrr_fifo_packet (txrr_fifo_packet[PW-1:0]),
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.edma_access (edma_access),
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.edma_packet (edma_packet[PW-1:0]),
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.ctrlmode_bypass (ctrlmode_bypass),
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.ctrlmode (ctrlmode[3:0]),
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.etx_rd_wait (etx_rd_wait),
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.etx_wr_wait (etx_wr_wait),
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.etx_io_wait (etx_io_wait),
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.etx_cfg_wait (etx_cfg_wait));
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/************************************************************/
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/* CONFIGURATOIN PACKET */
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/************************************************************/
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/*ecfg_if AUTO_TEMPLATE (
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.\(.*\)_in (etx_\1[]),
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.\(.*\)_out (etx_cfg_\1[]),
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.mi_dout0 ({32'b0,mi_cfg_dout[31:0]}),
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.mi_dout1 ({32'b0,mi_dma_dout[31:0]}),
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.mi_dout2 ({32'b0,mi_mmu_dout[31:0]}),
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.clk (tx_lclk_div4),
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);
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*/
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defparam etx_cfgif.RX =0;
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ecfg_if etx_cfgif (.mi_dout3 (64'b0),
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/*AUTOINST*/
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// Outputs
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.wait_out (etx_cfg_wait), // Templated
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.mi_mmu_en (mi_mmu_en),
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.mi_dma_en (mi_dma_en),
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.mi_cfg_en (mi_cfg_en),
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.mi_we (mi_we),
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.mi_addr (mi_addr[14:0]),
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.mi_din (mi_din[63:0]),
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.access_out (etx_cfg_access), // Templated
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.packet_out (etx_cfg_packet[PW-1:0]), // Templated
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// Inputs
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.clk (tx_lclk_div4), // Templated
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.reset (reset),
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.access_in (etx_access), // Templated
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.packet_in (etx_packet[PW-1:0]), // Templated
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.mi_dout0 ({32'b0,mi_cfg_dout[31:0]}), // Templated
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.mi_dout1 ({32'b0,mi_dma_dout[31:0]}), // Templated
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.mi_dout2 ({32'b0,mi_mmu_dout[31:0]}), // Templated
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.wait_in (etx_wait)); // Templated
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/************************************************************/
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/* ETX CONFIGURATION REGISTERS */
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/************************************************************/
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/*ecfg_tx AUTO_TEMPLATE (.mi_dout (mi_cfg_dout[DW-1:0]),
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.mi_en (mi_cfg_en),
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.clk (tx_lclk_div4),
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);
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*/
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assign tx_status[15:0] = {2'b0, //15:14
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etx_rd_wait, //13
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etx_wr_wait, //12
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txrr_fifo_read, //11
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txrr_wait, //10
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txrr_access, //9
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txrd_fifo_read, //8
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txrd_wait, //7
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txrd_access, //6
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txwr_fifo_read, //5
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txwr_wait, //4
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txwr_access, //3
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txrr_fifo_full, //2
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txrd_fifo_full, //1
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txwr_fifo_full //0
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};
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ecfg_tx etx_cfg (
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/*AUTOINST*/
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// Outputs
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.mi_dout (mi_cfg_dout[DW-1:0]), // Templated
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.tx_enable (tx_enable),
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.mmu_enable (mmu_enable),
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.gpio_enable (gpio_enable),
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.tp_enable (tp_enable),
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.remap_enable (remap_enable),
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.gpio_data (gpio_data[8:0]),
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.ctrlmode (ctrlmode[3:0]),
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.ctrlmode_bypass (ctrlmode_bypass),
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.chipid (chipid[11:0]),
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// Inputs
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.reset (reset),
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.clk (tx_lclk_div4), // Templated
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.mi_en (mi_cfg_en), // Templated
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.mi_we (mi_we),
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.mi_addr (mi_addr[RFAW+1:0]),
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.mi_din (mi_din[31:0]),
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.tx_status (tx_status[15:0]));
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/************************************************************/
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/* REMAPPING (SHIFT) DESTINATION ADDRESS */
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/************************************************************/
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/*etx_remap AUTO_TEMPLATE (
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.emesh_\(.*\)_in (etx_\1[]),
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.emesh_\(.*\)_out (etx_remap_\1[]),
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.remap_en (remap_enable),
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.remap_bypass (etx_rr),
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.clk (tx_lclk_div4),
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.emesh_wait (etx_wait),
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);
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*/
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etx_remap etx_remap (/*AUTOINST*/
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// Outputs
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.emesh_access_out(etx_remap_access), // Templated
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.emesh_packet_out(etx_remap_packet[PW-1:0]), // Templated
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// Inputs
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.clk (tx_lclk_div4), // Templated
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.reset (reset),
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.emesh_access_in(etx_access), // Templated
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.emesh_packet_in(etx_packet[PW-1:0]), // Templated
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.remap_en (remap_enable), // Templated
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.remap_bypass (etx_rr), // Templated
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.emesh_wait_in (etx_wait)); // Templated
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/************************************************************/
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/* EMMU */
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/************************************************************/
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/*emmu AUTO_TEMPLATE (
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.emesh_\(.*\)_in (etx_remap_\1[]),
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.emesh_\(.*\)_out (emmu_\1[]),
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.mmu_en (mmu_enable),
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.mmu_bp (etx_rr),
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.clk (tx_lclk_div4),
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.emmu_access_out (emmu_access),
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.emmu_packet_out (emmu_packet[PW-1:0]),
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.mi_dout (mi_mmu_dout[DW-1:0]),
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.emesh_wait_in (etx_wait),
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.emesh_packet_hi_out (),
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.mi_en (mi_mmu_en),
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);
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*/
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emmu etx_mmu (
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/*AUTOINST*/
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// Outputs
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.mi_dout (mi_mmu_dout[DW-1:0]), // Templated
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.emesh_access_out (emmu_access), // Templated
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.emesh_packet_out (emmu_packet[PW-1:0]), // Templated
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.emesh_packet_hi_out (), // Templated
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// Inputs
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.reset (reset),
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.clk (tx_lclk_div4), // Templated
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.mmu_en (mmu_enable), // Templated
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.mmu_bp (etx_rr), // Templated
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.mi_en (mi_mmu_en), // Templated
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.mi_we (mi_we),
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.mi_addr (mi_addr[14:0]),
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.mi_din (mi_din[DW-1:0]),
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.emesh_access_in (etx_remap_access), // Templated
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.emesh_packet_in (etx_remap_packet[PW-1:0]), // Templated
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.emesh_wait_in (etx_wait)); // Templated
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/************************************************************/
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/*ELINK PROTOCOL LOGIC */
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/************************************************************/
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/*etx_protocol AUTO_TEMPLATE (
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.etx_rd_wait (etx_rd_wait),
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.etx_wr_wait (etx_wr_wait),
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|
.etx_\(.*\) (emmu_\1[]),
|
|
.etx_wait (etx_wait),
|
|
.etx_io_wait (etx_io_wait),
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|
);
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|
*/
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|
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|
defparam etx_protocol.ID=ID;
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|
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etx_protocol etx_protocol ( .clk (tx_lclk_div4),
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|
/*AUTOINST*/
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|
// Outputs
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|
.etx_rd_wait (etx_rd_wait), // Templated
|
|
.etx_wr_wait (etx_wr_wait), // Templated
|
|
.etx_wait (etx_wait), // Templated
|
|
.etx_io_wait (etx_io_wait), // Templated
|
|
.tx_frame_par (tx_frame_par[7:0]),
|
|
.tx_data_par (tx_data_par[63:0]),
|
|
// Inputs
|
|
.reset (reset),
|
|
.testmode (testmode),
|
|
.etx_access (emmu_access), // Templated
|
|
.etx_packet (emmu_packet[PW-1:0]), // Templated
|
|
.tx_enable (tx_enable),
|
|
.tp_enable (tp_enable),
|
|
.gpio_enable (gpio_enable),
|
|
.gpio_data (gpio_data[8:0]),
|
|
.chipid (chipid[11:0]),
|
|
.tx_rd_wait (tx_rd_wait),
|
|
.tx_wr_wait (tx_wr_wait));
|
|
|
|
|
|
/***********************************************************/
|
|
/*ELINK TRANSMIT I/O LOGIC */
|
|
/***********************************************************/
|
|
|
|
etx_io etx_io (
|
|
/*AUTOINST*/
|
|
// Outputs
|
|
.txo_lclk_p (txo_lclk_p),
|
|
.txo_lclk_n (txo_lclk_n),
|
|
.txo_frame_p (txo_frame_p),
|
|
.txo_frame_n (txo_frame_n),
|
|
.txo_data_p (txo_data_p[7:0]),
|
|
.txo_data_n (txo_data_n[7:0]),
|
|
.tx_wr_wait (tx_wr_wait),
|
|
.tx_rd_wait (tx_rd_wait),
|
|
// Inputs
|
|
.reset (reset),
|
|
.txi_wr_wait_p (txi_wr_wait_p),
|
|
.txi_wr_wait_n (txi_wr_wait_n),
|
|
.txi_rd_wait_p (txi_rd_wait_p),
|
|
.txi_rd_wait_n (txi_rd_wait_n),
|
|
.tx_lclk_div4 (tx_lclk_div4),
|
|
.tx_lclk (tx_lclk),
|
|
.tx_lclk90 (tx_lclk90),
|
|
.tx_frame_par (tx_frame_par[7:0]),
|
|
.tx_data_par (tx_data_par[63:0]));
|
|
|
|
|
|
endmodule // elink
|
|
// Local Variables:
|
|
// verilog-library-directories:("." "../../emmu/hdl" "../../memory/hdl" "../../edma/hdl/")
|
|
// End:
|
|
|
|
|
|
/*
|
|
Copyright (C) 2015 Adapteva, Inc.
|
|
|
|
Contributed by Andreas Olofsson <andreas@adapteva.com>
|
|
|
|
This program is free software: you can redistribute it and/or modify
|
|
it under the terms of the GNU General Public License as published by
|
|
the Free Software Foundation, either version 3 of the License, or
|
|
(at your option) any later version.This program is distributed in the hope
|
|
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
|
|
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
GNU General Public License for more details. You should have received a copy
|
|
of the GNU General Public License along with this program (see the file
|
|
COPYING). If not, see <http://www.gnu.org/licenses/>.
|
|
*/
|