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46 lines
1.4 KiB
Verilog
46 lines
1.4 KiB
Verilog
//#############################################################################
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//# Function: Binary adder #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_add
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#(parameter N = 32, // block width
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parameter SYN = "TRUE", // synthesizable
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parameter TYPE = "DEFAULT" // implementation type
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)
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(//inputs
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input [N-1:0] a, // first operand
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input [N-1:0] b, // second operand
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input [N-1:0] k, // carrry kill signal (active high)
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input cin,// carry in
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//outputs
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output [N-1:0] sum,// sum
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output [N-1:0] carry,// complete carry out vector
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output cout// carry out from msb
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);
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generate
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if(SYN == "TRUE") begin
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assign {cout,sum[N-1:0]} = a[N-1:0] + b[N-1:0] + cin;
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//TODO: FIX
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assign carry = 'b0;
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end
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else begin
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asic_add #(.TYPE(TYPE),
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.N(N))
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asic_add (// Outputs
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.sum (sum[N-1:0]),
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.carry (carry[N-1:0]),
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.cout (cout),
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// Inputs
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.a (a[N-1:0]),
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.b (b[N-1:0]),
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.k (k[N-1:0]),
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.cin (cin));
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end
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endgenerate
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endmodule
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