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34 lines
1.0 KiB
Verilog
34 lines
1.0 KiB
Verilog
//#############################################################################
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//# Function: Statically configured arbiter #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_arbiter
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#( parameter N = 1,
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parameter TYPE = "FIXED" // or ROUNDROBIN, FAIR
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)
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(
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input [N-1:0] requests, //request vector
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output [N-1:0] grants //grant (one hot)
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);
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wire [N-1:0] waitmask;
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genvar j;
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generate
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if(TYPE=="FIXED")
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begin : arbiter_fixed
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assign waitmask[0] = 1'b0;
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for (j=N-1; j>=1; j=j-1)
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begin : gen_arbiter
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assign waitmask[j] = |requests[j-1:0];
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end
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end
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endgenerate
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//grant circuit
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assign grants[N-1:0] = requests[N-1:0] & ~waitmask[N-1:0];
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endmodule // oh_arbiter
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