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34 lines
1.2 KiB
Verilog
34 lines
1.2 KiB
Verilog
//#############################################################################
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//# Function: Parametrized clock mux (N to 1) #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_clockmux
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#(parameter N = 2, // number of clock inputs)
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parameter SYN = "TRUE", // synthesizable (or not)
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parameter TYPE = "DEFAULT" // implementation type
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)
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(
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input [N-1:0] en, // one hot enable vector (needs to be stable!)
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input [N-1:0] clkin, // one hot clock inputs (only one is active!)
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output clkout // clock output
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);
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generate
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if(SYN == "TRUE") begin
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assign clkout = |(clkin[N-1:0] & en[N-1:0]);
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end
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else begin
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asic_clockmux #(.TYPE(TYPE),
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.N(N))
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asic_clockmux(// Outputs
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.clkout (clkout),
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// Inputs
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.en (en[N-1:0]),
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.clkin (clkin[N-1:0]));
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end
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endgenerate
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endmodule
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