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41 lines
1.3 KiB
Verilog
41 lines
1.3 KiB
Verilog
//#############################################################################
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//# Function: 2:1 Clock Mux #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_clockmux2
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#(parameter N = 1, // vector width
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parameter SYN = "TRUE", // synthesizable (or not)
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parameter TYPE = "DEFAULT" // implementation type
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)
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(
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input [N-1:0] en0, // clkin0 enable (stable high)
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input [N-1:0] en1, // clkin1 enable (stable high)
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input [N-1:0] clkin0, // clock input
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input [N-1:0] clkin1, // clock input
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output [N-1:0] clkout // clock output
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);
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generate
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if(SYN == "TRUE") begin
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assign clkout[N-1:0] = (en0[N-1:0] & clkin0[N-1:0]) |
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(en1[N-1:0] & clkin1);
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end
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else begin
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genvar i;
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for (i=0;i<N;i=i+1) begin
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asic_clockmux2 #(.TYPE(TYPE))
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asic_clockmux2(// Outputs
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.clkout (clkout[N-1:0]),
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// Inputs
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.en0 (en0[N-1:0]),
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.en1 (en1[N-1:0]),
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.clkin0 (clkin0[N-1:0]),
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.clkin1 (clkin1[N-1:0]));
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end
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end
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endgenerate
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endmodule
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