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oh/stdlib/rtl/oh_dffqn.v
Andreas.Olofsson e631bfe3f1 Fixing naming error
-The directory should contain rtl only.
-HDL is too broad a term
2022-06-22 11:04:54 -04:00

18 lines
602 B
Verilog

//#############################################################################
//# Function: Positive edge-triggered inverting static D-type flop-flop #
//# Copyright: OH Project Authors. ALl rights Reserved. #
//# License: MIT (see LICENSE file in OH repository) #
//#############################################################################
module oh_dffqn #(parameter DW = 1) // array width
(
input [DW-1:0] d,
input [DW-1:0] clk,
output reg [DW-1:0] qn
);
always @ (posedge clk)
qn <= ~d;
endmodule