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97 lines
2.9 KiB
Verilog
97 lines
2.9 KiB
Verilog
//#############################################################################
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//# Function: Clock domain crossing FIFO #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_fifo_cdc
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#(parameter N = 32, // fifo width
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parameter DEPTH = 32, // fifo depth
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parameter TARGET = "DEFAULT", // synthesis/sim target
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parameter AW = $clog2(DEPTH) // rd_count width (derived)
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)
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(
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input nreset, // async active low reset
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//Write Side
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input clk_in, // write clock
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input valid_in, // write valid
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input [N-1:0] packet_in, // write packet
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output ready_out, // write pushback
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//Read Side
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input clk_out, // read clock
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output reg valid_out, // read valid
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output [N-1:0] packet_out, // read packet
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input ready_in, // read pushback
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//Status
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output prog_full, // fifo is half full
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output full, // fifo is full
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output empty // fifo is empty
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);
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// wire declarations
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wire wr_en;
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wire rd_en;
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wire rd_empty;
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wire wr_almost_full;
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wire wr_full;
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wire wr_prog_full;
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wire nreset_out;
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// FIFO control logic
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assign wr_en = valid_in;
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assign rd_en = ~empty & ready_in;
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assign ready_out = ~(wr_almost_full | wr_full | wr_prog_full);
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//async asser, sync deassert of reset
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oh_rsync #(.TARGET(TARGET))
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sync_reset(.nrst_out (nreset_out),
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.clk (clk_out),
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.nrst_in (nreset));
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//align valid signal with FIFO read delay
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always @ (posedge clk_out or negedge nreset_out)
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if(!nreset_out)
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valid_out <= 1'b0;
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else if(ready_in)
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valid_out <= rd_en;
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// parametric async fifo
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oh_fifo_async #(.TARGET(TARGET),
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.N(N),
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.DEPTH(DEPTH))
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oh_fifo_async (
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.rd_clk (clk_out),
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.rd_dout (packet_out[N-1:0]),
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.wr_clk (clk_in),
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.wr_din (packet_in[N-1:0]),
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.memconfig (8'b0),
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.memrepair (8'b0),
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.shutdown (1'b0),
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.vddio (1'b1),
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.vdd (1'b0),
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.vss (1'b0),
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.bist_en (1'b0),
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.bist_we (1'b0),
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.bist_wem ({(N){1'b0}}),
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.bist_addr ({(AW){1'b0}}),
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.bist_din ({(N){1'b0}}),
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.bist_dout (),
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.wr_count (),
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.rd_count (),
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/*AUTOINST*/
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// Outputs
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.wr_full (wr_full),
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.wr_almost_full (wr_almost_full),
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.wr_prog_full (wr_prog_full),
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.rd_empty (rd_empty),
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// Inputs
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.nreset (nreset),
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.wr_en (wr_en),
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.rd_en (rd_en));
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endmodule // oh_fifo_cdc
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// Local Variables:
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// verilog-library-directories:("." "../fpga/" "../dv")
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// End:
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