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70 lines
1.8 KiB
Verilog
70 lines
1.8 KiB
Verilog
//#############################################################################
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//# Function: Dual data rate input buffer (2 cycle delay) #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_iddr
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#(parameter N = 1, // vector width
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parameter SYN = "TRUE", // synthesizable (or not)
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parameter TYPE = "DEFAULT" // scell type/size
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)
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(
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input clk, // clock
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input en0, // 1st cycle enable
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input en1, // 2nd cycle enable
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input [N-1:0] in, // data input sampled on both edges of clock
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output reg [2*N-1:0] out // iddr aligned
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);
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generate
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if(SYN == "TRUE") begin
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//regs("sl"=stable low, "sh"=stable high)
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reg [N-1:0] in_sl;
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reg [N-1:0] in_sh;
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reg en0_negedge;
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//########################
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// Pipeline valid for negedge
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//########################
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always @ (negedge clk)
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en0_negedge <= en0;
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//########################
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// Dual edge sampling
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//########################
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always @ (posedge clk)
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if(en0)
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in_sl[N-1:0] <= in[N-1:0];
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always @ (negedge clk)
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if(en0_negedge)
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in_sh[N-1:0] <= in[N-1:0];
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//########################
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// Aign pipeline
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//########################
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always @ (posedge clk)
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if(en1)
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out[2*N-1:0] <= {in_sh[N-1:0],
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in_sl[N-1:0]};
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end
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else begin
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for (i=0;i<N;i=i+1) begin
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asic_iddr #(.TYPE(TYPE))
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asic_iddr(// Outputs
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.out (out[2*N-1:0]),
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// Inputs
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.clk (clk),
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.en0 (en0),
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.en1 (en1),
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.in (in[N-1:0]));
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end
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end
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endgenerate
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endmodule // oh_iddr
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