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38 lines
1.1 KiB
Verilog
38 lines
1.1 KiB
Verilog
//#############################################################################
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//# Function: Achive high latch #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_lat1
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#(parameter N = 1, // number of sync stages
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parameter SYN = "TRUE", // synthesizable (or not)
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parameter TYPE = "DEFAULT" // scell type/size
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)
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(input clk, // clk
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input [N-1:0] in, // input data
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output [N-1:0] out // output data
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);
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generate
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if(SYN == "TRUE") begin
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reg [N-1:0] out_reg;
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always @ (clk or in)
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if (clk)
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out_reg[N-1:0] <= in[N-1:0];
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assign out[N-1:0] = out_reg[N-1:0];
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end
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else begin
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for (i=0;i<N;i=i+1) begin
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asic_lat1 #(.TYPE(TYPE))
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asic_lat1 (.clk(clk),
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.in(in[i]),
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.out(out[i]));
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end
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end
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endgenerate
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endmodule // oh_lat1
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