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19 lines
631 B
Verilog
19 lines
631 B
Verilog
//#############################################################################
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//# Function: 4 Input Nand Gate #
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//# Copyright: OH Project Authors. ALl rights Reserved. #
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//# License: MIT (see LICENSE file in OH repository) #
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//#############################################################################
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module oh_nand4 #(parameter DW = 1 ) // array width
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(
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input [DW-1:0] a,
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input [DW-1:0] b,
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input [DW-1:0] c,
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input [DW-1:0] d,
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output [DW-1:0] z
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);
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assign z = ~(a & b & c & d);
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endmodule
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