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27 lines
1.1 KiB
Verilog
27 lines
1.1 KiB
Verilog
//#############################################################################
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//# Function: Phase Locked Loop #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_pll #(parameter N = 8) // number of clocks
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( input clkin, // primary clock input
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input nreset, // async active low reset
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input clkfb, // feedback clock
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input pll_en, // enable pll
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input [N*8-1:0] clkdiv, // clock divider settings (per clock)
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input [N*16-1:0] clkphase, // clock phase setting (rise/fall edge)
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input [7:0] clkmult, // feedback clock multiplier
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output [N-1:0] clkout, // output clocks
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output locked // PLL locked status
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);
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`ifdef TARGET_SIM
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//insert PLL simulation model
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`endif
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endmodule // oh_pll
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