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39 lines
1.2 KiB
Verilog
39 lines
1.2 KiB
Verilog
//#############################################################################
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//# Function: Reset synchronizer (async assert, sync deassert) #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_rsync
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#(parameter SYNCPIPE = 2, // number of sync stages
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parameter TARGET = "DEFAULT" // scell type/size
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)
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(
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input clk,
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input nrst_in,
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output nrst_out
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);
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generate
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if(TARGET == "DEFAULT")
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begin
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reg [SYNCPIPE-1:0] sync_pipe;
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always @ (posedge clk or negedge nrst_in)
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if(!nrst_in)
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sync_pipe[SYNCPIPE-1:0] <= 'b0;
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else
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sync_pipe[SYNCPIPE-1:0] <= {sync_pipe[SYNCPIPE-2:0],1'b1};
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assign nrst_out = sync_pipe[SYNCPIPE-1];
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end
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else
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begin
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asic_rsync #(.TARGET(TARGET),
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.SYNCPIPE(SYNCPIPE))
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asic_rsync (.clk(clk),
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.nrst_in(nrst_in),
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.nrst_out(nrst_out));
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end
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endgenerate
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endmodule // oh_rsync
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