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25 lines
831 B
Verilog
25 lines
831 B
Verilog
//#############################################################################
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//# Function: Positive edge-triggered static inverting D-type flop-flop with #
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// async active low set and scan input #
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//# Copyright: OH Project Authors. ALl rights Reserved. #
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//# License: MIT (see LICENSE file in OH repository) #
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//#############################################################################
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module oh_sdffsqn #(parameter DW = 1) // array width
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(
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input [DW-1:0] d,
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input [DW-1:0] si,
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input [DW-1:0] se,
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input [DW-1:0] clk,
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input [DW-1:0] nset,
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output reg [DW-1:0] qn
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);
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always @ (posedge clk or negedge nset)
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if(!nset)
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qn <= 'b0;
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else
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qn <= se ? ~si : ~d;
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endmodule
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