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54 lines
1.7 KiB
Verilog
54 lines
1.7 KiB
Verilog
//#############################################################################
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//# Function: Barrel shifter #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_shift
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#(parameter N = 32, // Operator width (8,16,32,64,128)
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parameter S = $clog2(N), // stages=shift width
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parameter SYN = "TRUE" // TRUE is synthesizable
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)
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(
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input [N-1:0] in, // data to be shifted
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input arithmetic, // shifts in in[N-1] instead of 0
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input right, // shift right (default is left shift)
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input [S-1:0] shamt, // shift amount (unsigned)
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output [N-1:0] out //shifted output
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);
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generate
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if(SYN=="TRUE") begin: gbehavioral
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wire [2*N-1:0] in_sext;
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wire [N-1:0] sr_result;
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wire [N-1:0] sl_result;
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assign shift_in = arithmetic & in[N-1];
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assign in_sext[2*N-1:0] = {{(N){shift_in}},in[N-1:0]};
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assign sr_result[N-1:0] = in_sext[2*N-1:0] >> shamt[S-1:0];
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assign sl_result[N-1:0] = in[N-1:0] << shamt[S-1:0];
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assign out[N-1:0] = right ? sr_result[N-1:0] :
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sl_result[N-1:0];
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end // block: gbehavioral
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else begin
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asic_shift #(.TYPE(TYPE),
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.N(N))
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asic_shift (// Outputs
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.out (out[N-1:0]),
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// Inputs
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.in (in[N-1:0]),
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.arithmetic (arithmetic),
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.right (right),
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.shamt (shamt[S-1:0]));
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end
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endgenerate
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endmodule
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