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277 lines
8.5 KiB
Verilog
277 lines
8.5 KiB
Verilog
module dv_elink(/*AUTOARG*/
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// Outputs
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dut_passed, dut_failed, dut_rd_wait, dut_wr_wait, dut_access,
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dut_packet,
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// Inputs
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clk, reset, ext_access, ext_packet, ext_rd_wait, ext_wr_wait
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);
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parameter AW = 32;
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parameter DW = 32;
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parameter CW = 2; //number of clocks to send int
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parameter IDW = 12;
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parameter PW = 104;
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//Basic
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input [CW-1:0] clk; // Core clock
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input reset; // Reset
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output dut_passed; // Indicates passing test
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output dut_failed; // Indicates failing test
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//Input Transaction
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input ext_access;
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input [PW-1:0] ext_packet;
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output dut_rd_wait;
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output dut_wr_wait;
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//Output Transaction
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output dut_access;
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output [PW-1:0] dut_packet;
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input ext_rd_wait;
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input ext_wr_wait;
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/*AUTOINPUT*/
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/*AUTOOUTPUT*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [7:0] data_n; // From elink of elink.v
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wire [7:0] data_p; // From elink of elink.v
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wire frame_n; // From elink of elink.v
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wire frame_p; // From elink of elink.v
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wire lclk_n; // From elink of elink.v
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wire lclk_p; // From elink of elink.v
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wire rd_wait_n; // From elink of elink.v
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wire rd_wait_p; // From elink of elink.v
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wire wr_wait_n; // From elink of elink.v
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wire wr_wait_p; // From elink of elink.v
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// End of automatics
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wire [3:0] colid;
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wire [3:0] rowid;
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wire mailbox_full;
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wire mailbox_not_empty;
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wire cclk_p, cclk_n;
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wire chip_resetb;
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wire emem_access;
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wire [PW-1:0] emem_packet;
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wire dut_access;
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wire [PW-1:0] dut_packet;
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wire rxrr_access;
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wire [PW-1:0] rxrr_packet;
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wire rxwr_access;
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wire [PW-1:0] rxwr_packet;
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wire rxrd_access;
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wire [PW-1:0] rxrd_packet;
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wire txrr_access;
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wire [PW-1:0] txrr_packet;
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wire txwr_access;
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wire [PW-1:0] txwr_packet;
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wire txrd_access;
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wire [PW-1:0] txrd_packet;
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wire txrd_wait;
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wire txwr_wait;
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wire txrr_wait;
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wire rxrr_wait;
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wire emem_wait;
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wire rxrd_wait;
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reg [31:0] etime;
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wire itrace = 1'b1;
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//Clocks
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wire clkin = clk[0]; //for pll-->cclk, rxclk, txclk
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//Splitting transaction into read/write path
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//Read path
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assign txrd_access = ext_access & ~ext_packet[1];
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assign txrd_packet[PW-1:0] = ext_packet[PW-1:0];
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//Write path
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assign txwr_access = ext_access & ext_packet[1];
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assign txwr_packet[PW-1:0] = ext_packet[PW-1:0];
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//TX Pushback
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assign dut_rd_wait = txrd_wait;
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assign dut_wr_wait = txwr_wait;
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//Getting results back
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assign dut_access = rxrr_access;
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assign dut_packet[PW-1:0] = rxrr_packet[PW-1:0];
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/*elink AUTO_TEMPLATE (
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// Outputs
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.txo_\(.*\) (\1[]),
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.rxi_\(.*\) (\1[]),
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.rxo_\(.*\) (\1[]),
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.txi_\(.*\) (\1[]),
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.\(.*\)_clk (clk[1]),
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);
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*/
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defparam elink.TXID = 12'h810;
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defparam elink.RXID = 12'h820;
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elink elink (.hard_reset (reset),
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.mailbox_not_empty (mailbox_not_empty),
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.mailbox_full (mailbox_full),
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.chip_resetb (chip_resetb),
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.colid (colid[3:0]),
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.rowid (rowid[3:0]),
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.cclk_p (cclk_p),
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.cclk_n (cclk_n),
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.clkin (clkin),
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.clkbypass ({clkin,clkin,clkin}),
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.rxrd_access (rxrd_access),//to emem
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.rxrd_packet (rxrd_packet[PW-1:0]),
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.rxwr_access (rxwr_access),//to emem
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.rxwr_packet (rxwr_packet[PW-1:0]),
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.rxrr_access (rxrr_access),//to ext
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.rxrr_packet (rxrr_packet[PW-1:0]),
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.txrd_access (txrd_access),//from ext
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.txrd_packet (txrd_packet[PW-1:0]),
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.txwr_access (txwr_access),//from ext
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.txwr_packet (txwr_packet[PW-1:0]),
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.txrd_wait (txrd_wait),
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.txrr_wait (txrr_wait),
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.txwr_wait (txwr_wait),
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.rxrr_wait (ext_wr_wait),
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.rxwr_wait (1'b0),
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/*AUTOINST*/
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// Outputs
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.rxo_wr_wait_p (wr_wait_p), // Templated
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.rxo_wr_wait_n (wr_wait_n), // Templated
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.rxo_rd_wait_p (rd_wait_p), // Templated
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.rxo_rd_wait_n (rd_wait_n), // Templated
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.txo_lclk_p (lclk_p), // Templated
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.txo_lclk_n (lclk_n), // Templated
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.txo_frame_p (frame_p), // Templated
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.txo_frame_n (frame_n), // Templated
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.txo_data_p (data_p[7:0]), // Templated
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.txo_data_n (data_n[7:0]), // Templated
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// Inputs
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.rxi_lclk_p (lclk_p), // Templated
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.rxi_lclk_n (lclk_n), // Templated
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.rxi_frame_p (frame_p), // Templated
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.rxi_frame_n (frame_n), // Templated
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.rxi_data_p (data_p[7:0]), // Templated
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.rxi_data_n (data_n[7:0]), // Templated
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.txi_wr_wait_p (wr_wait_p), // Templated
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.txi_wr_wait_n (wr_wait_n), // Templated
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.txi_rd_wait_p (rd_wait_p), // Templated
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.txi_rd_wait_n (rd_wait_n), // Templated
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.rxwr_clk (clk[1]), // Templated
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.rxrd_clk (clk[1]), // Templated
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.rxrd_wait (rxrd_wait),
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.rxrr_clk (clk[1]), // Templated
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.txwr_clk (clk[1]), // Templated
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.txrd_clk (clk[1]), // Templated
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.txrr_clk (clk[1]), // Templated
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.txrr_access (txrr_access),
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.txrr_packet (txrr_packet[PW-1:0]));
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assign emem_access = rxwr_access | rxrd_access;
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assign emem_packet[PW-1:0] = rxwr_access ? rxwr_packet[PW-1:0]:
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rxrd_packet[PW-1:0];
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assign rxrd_wait = emem_wait | rxwr_access;
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/*ememory AUTO_TEMPLATE (
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// Outputs
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.\(.*\)_out (txrr_\1[]),
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.\(.*\)_in (emem_\1[]),
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.wait_out (emem_wait),
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);
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*/
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ememory emem (.wait_in (1'b0), //only one read at a time, set to zero for no1
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.clk (clk[1]),
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.wait_out (emem_wait),
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/*AUTOINST*/
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// Outputs
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.access_out (txrr_access), // Templated
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.packet_out (txrr_packet[PW-1:0]), // Templated
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// Inputs
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.reset (reset),
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.access_in (emem_access), // Templated
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.packet_in (emem_packet[PW-1:0])); // Templated
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//Transaction Monitor
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always @ (posedge clkin or posedge reset)
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if(reset)
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etime[31:0] <= 32'b0;
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else
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etime[31:0] <= etime[31:0]+1'b1;
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/*emesh_monitor AUTO_TEMPLATE (
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// Outputs
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.emesh_\(.*\) (@"(substring vl-cell-name 0 3)"_\1[]),
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);
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*/
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emesh_monitor #(.NAME("stimulus")) ext_monitor (.emesh_wait ((dut_rd_wait | dut_wr_wait)),//TODO:fix collisions
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.clk (clk[1]),
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/*AUTOINST*/
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// Inputs
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.reset (reset),
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.itrace (itrace),
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.etime (etime[31:0]),
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.emesh_access (ext_access), // Templated
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.emesh_packet (ext_packet[PW-1:0])); // Templated
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emesh_monitor #(.NAME("dut")) dut_monitor (.emesh_wait (1'b0),
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.clk (clk[1]),
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/*AUTOINST*/
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// Inputs
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.reset (reset),
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.itrace (itrace),
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.etime (etime[31:0]),
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.emesh_access (dut_access), // Templated
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.emesh_packet (dut_packet[PW-1:0])); // Templated
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emesh_monitor #(.NAME("emem")) mem_monitor (.emesh_wait (1'b0),
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.clk (clk[1]),
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.emesh_access (emem_access),
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.emesh_packet (emem_packet[PW-1:0]),
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/*AUTOINST*/
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// Inputs
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.reset (reset),
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.itrace (itrace),
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.etime (etime[31:0]));
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endmodule // dv_elink
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// Local Variables:
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// verilog-library-directories:("." "../hdl" "../../memory/hdl")
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// End:
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/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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